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8V49N211 데이터시트 PDF




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부품번호 8V49N211 기능
기능 Clock Generator
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8V49N211 데이터시트, 핀배열, 회로
Clock Generator for Broadcom Processor
8V49N211
DATA SHEET
General Description
The 8V49N211 is a high-performance PLL-based clock generator
designed to interface with Broadcom XLP2xxx processors. The
8V49N211 has one 25MHz crystal input to generate output
frequencies to support XLP Core/DDR3, USB, SGMII/XAUI and
PCIe reference clocks in a single chip. The 8V49N211 low jitter VCO
easily meets PCI Express Gen 1, 2 and 3 requirements.
IDT’s Fourth Generation FemtoClock® NG technology has best in
class phase noise performance.
Features
Fourth Generation FemtoClock® NG PLL technology
Two LVCMOS clock outputs for core/DDR3 at 133.33MHz or
66.66MHz
One LVDS clock output for USB at 100MHz
Three LVDS clock outputs for SGMII/XAUI at 125MHz
Five HCSL clock outputs for PCIe at 100MHz
Crystal oscillator interface designed for 25MHz (CL = 12pF)
frequency, IDT Part #603-25-173
PCI Express Gen 1 (2.5Gb/s), Gen 2 (5Gb/s) and Gen 3 (8Gb/s)
jitter compliant
Full 3.3V operating supply voltage
Lead-free (RoHS 6) packaging
-40°C to 85°C ambient operating temperature
Pin Assignment
G ND
VS S O_A
QA1
QA0
V DDO_A
FSEL
BYPAS S
V DD
G ND
OE _1
OE _2
OE _3
OE _4
G ND
42 41 40 39 38 37 36 35 34 33 32 31 30 29
43 28
44 27
45 26
46 25
47 24
48
49 8V49N211
50
23
22
21
51 20
52 19
53 18
54 17
55 16
56 15
1 2 3 4 5 6 7 8 9 10 11 12 13 14
V DDO_C
nQC 4
QC4
nQC 3
QC3
VS S O_C
nQC 2
QC2
V DDO_C
nQC 1
QC1
nQC 0
QC0
V DDO_C
56 Lead 8mm x 8mm VFQFN
REVISION B 05/29/15
1 ©2015 INTEGRATED DEVICE TECHNOLOGY, INC.




8V49N211 pdf, 반도체, 판매, 대치품
8V49N211 DATA SHEET
Number
Name
Type
Description
49
BYPASS
Input
Pulldown PLL Bypass mode select pin. See Table 3C for function.
LVCMOS/LVTTL interface levels.
50
52, 53,
54, 55
VDD
OE_1, OE_2
OE_3, OE_4
Power
Input
Pullup
Power supply pin.
Output enable. LVCMOS/LVTTL interface levels. See “Table 3B. OE
Function Table”.
NOTE: Pulldown and Pullup refers to an internal input resistor. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
RPULLDOWN
RPULLUP
ROUT
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
QA[0:1]
Output Impedance
REFOUT
Test Conditions
XTAL_IN, XTAL_OUT not included
VDDO_A = 3.465V
VDDO_REFOUT = 3.465V
Minimum
Typical
3.5
51
51
14
30
Maximum
Units
pF
k
k
Function Tables
Table 3A. Frequency Select Table
FSEL
0 (default)
1
QAx outputs
133.33MHz
66.66MHz
Table 3B. OE Function Table
OEx
0
1(default)
Output State
High Impedance
Enabled
Table 3C. PLL BYPASS Function Table
BYPASS
Operation
1
PLL is bypassed. The reference frequency is divided by the selected output dividers in Bank A, Bank B,
Bank C. AC specifications do not apply in PLL BYPASS mode.
0 (default)
PLL is enabled. The reference frequency is multiplied by the PLL feedback divider and then divided by the
selected output dividers in Bank A, Bank B, Bank C.
REVISION B 05/29/15
4 CLOCK GENERATOR FOR BROADCOM PROCESSOR

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8V49N211 전자부품, 판매, 대치품
8V49N211 DATA SHEET
AC Electrical Characteristics
Table 6A. LVCMOS AC Electrical Characteristics, VDD_X = VDDO_A = VDDO_REFOUT = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output
Frequency
REF_OUT
QA[0:1]
QA[0:1]
FSEL = 1
FSEL = 0
25
66.66
133.33
MHz
MHz
MHz
tJIT
RMS Phase Jitter
(Random); NOTE 1
fOUT = 133.33MHz,
Integration Range (12kHz to 20MHz)
fOUT = 66.66MHz,
Integration Range (12kHz to 20MHz)
0.27 0.40
0.29 0.45
ps
ps
n(100)
100Hz from Carrier
-98 dBc/Hz
n(1k)
n(10k)
n(100k)
n(1M)
Single-side Band Phase
Noise for fOUT =
133.33MHz
1kHz from Carrier
10kHz from Carrier
100kHz from Carrier
1MHz from Carrier
-122
-134
-138
-145
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
n(10M)
10MHz from Carrier
-153
dBc/Hz
tJIT(cc)
tsk(o)
Cycle-to-Cycle Jitter;
NOTE 2
Output Skew;
NOTE 2, 3
QA[0:1]
fOUT = 133.33MHz
fOUT = 66.66MHz
35 ps
40 ps
30 ps
odc
Output
Duty Cycle
REF_OUT
QA[0:1]
47 53 %
40 60 %
tR / tF
Output Rise/ Fall Time
20% to 80%
275 800 ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: VDD_X denotes, VDD, VDDD, VDD_XTAL.
NOTE: Characterized using IDT/ Fox Part #603-25-173 crystal.
NOTE 1: Refer to the phase noise plot.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
REVISION B 05/29/15
7 CLOCK GENERATOR FOR BROADCOM PROCESSOR

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부품번호상세설명 및 기능제조사
8V49N211

Clock Generator

Integrated Device Technology
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