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PDF SN74LS197 Data sheet ( Hoja de datos )
| Número de pieza | SN74LS197 | |
| Descripción | 4-STAGE PRESETTABLE RIPPLE COUNTERS | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SN74LS197 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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4-STAGE PRESETTABLE
RIPPLE COUNTERS
The SN54/74LS196 decade counter is partitioned into divide-by-two and di-
vide-by-five sections which can be combined to count either in BCD (8, 4, 2, 1)
sequence or in a bi-quinary mode producing a 50% duty cycle output. The
SN54/74LS197 contains divide-by-two and divide-by-eight sections which
can be combined to form a modulo-16 binary counter. Low Power Schottky
technology is used to achieve typical count rates of 70 MHz and power dis-
sipation of only 80 mW.
Both circuit types have a Master Reset (MR) input which overrides all other
inputs and asynchronously forces all outputs LOW. A Parallel Load input (PL)
overrides clocked operations and asynchronously loads the data on the Par-
allel Data inputs (Pn) into the flip-flops. This preset feature makes the circuits
usable as programmable counters. The circuits can also be used as 4-bit
latches, loading data from the Parallel Data inputs when PL is LOW and stor-
ing the data when PL is HIGH.
• Low Power Consumption — Typically 80 mW
• High Counting Rates — Typically 70 MHz
• Choice of Counting Modes — BCD, Bi-Quinary, Binary
• Asynchronous Presettable
• Asynchronous Master Reset
• Easy Multistage Cascading
• Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC MR Q3 P3 P1 Q1 CP0
14 13 12 11 10 9
8
1234567
PL Q2 P2 P0 Q0 CP1 GND
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
PIN NAMES
LOADING (Note a)
HIGH
LOW
CP0
Clock (Active LOW Going Edge)
1.0 U.L.
1.5 U.L.
Input to Divide-by-Two Section
CP1 (LS196) Clock (Active LOW Going Edge)
Input to Divide-by-Five Section
2.0 U.L.
1.75 U.L.
CP1 (LS197) Clock (Active LOW Going Edge)
Input to Divide-by-Eight Section
1.0 U.L.
0.8 U.L.
MR
Master Reset (Active LOW) Input
1.0 U.L.
0.5 U.L.
PL
Parallel Load (Active LOW) Input
0.5 U.L.
0.25 U.L.
P0–P3
Q0–Q3
Data Inputs
Outputs (Notes b, c)
0.5 U.L.
10 U.L.
0.25 U.L.
5 (2.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
c. In addition to loading shown, Q0 can also drive CP1.
FAST AND LS TTL DATA
5-372
SN54/74LS196
SN54/74LS197
4-STAGE PRESETTABLE
RIPPLE COUNTERS
LOW POWER SCHOTTKY
14
1
J SUFFIX
CERAMIC
CASE 632-08
14
1
N SUFFIX
PLASTIC
CASE 646-06
14
1
D SUFFIX
SOIC
CASE 751A-02
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
1 4 10 3 11
8 CP0 PL P0 P1 P2 P3
6 CP1 MR Q0 Q1 Q2 Q3
13 5 9 2 12
VCC = PIN 14
GND = PIN 7
1 page  
SN54/74LS196 • SN54/74LS197
AC CHARACTERISTICS (TA = 25°C)
Symbol
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
Parameter
Maximum Clock Frequency
CP0 Input to
Q0 Output
CP1 Input to
Q1 Output
CP1 Input to
Q2 Output
CP1 Input to
Q3 Output
Data to Output
PL Input to
Any Output
MR Input to Any Output
AC SETUP REQUIREMENTS (TA = 25°C)
Symbol
tW
tW
tW
tW
ts
ts
th
th
trec
Parameter
CP0 Pulse Width
CP1 Pulse Width
PL Pulse Width
MR Pulse Width
Data Input Setup Time — HIGH
Data Input Setup Time — LOW
Data Hold Time — HIGH
Data Hold Time — LOW
Recovery Time
Limits
LS196
LS197
Min Typ Max Min Typ Max
30 40
30 40
8.0 15
13 20
8.0 15
14 21
16 24
22 33
12 19
23 35
38 57
41 62
34 51
42 63
12 18
30 45
55 78
63 95
20 30
29 44
18 27
29 44
27 41
30 45
26 39
30 45
34 51
34 51
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
Limits
LS196
LS197
Min Typ Max Min Typ Max
20 20
30 30
20 20
15 15
10 10
15 15
10 10
10 10
30 30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions
VCC = 5.0 V
CL = 15 pF
Test Conditions
VCC = 5.0 V
DEFINITIONS OF TERMS
SETUP TIME (ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from HIGH to LOW in order to be recog-
nized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from HIGH to LOW that the logic level must
be maintained at the input in order to ensure continued recog-
nition. A negative HOLD TIME indicates that the correct logic
level may be released prior to the clock transition from HIGH to
LOW and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from HIGH to LOW in order to recognize and transfer
LOW Data to the Q outputs.
FAST AND LS TTL DATA
5-376
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet SN74LS197.PDF ] | |
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