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PDF MCP1710 Data sheet ( Hoja de datos )
| Número de pieza | MCP1710 | |
| Descripción | Ultra Low Quiescent Current LDO Regulator | |
| Fabricantes | Microchip | |
| Logotipo |  |
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MCP1710
Ultra Low Quiescent Current LDO Regulator
Features
• Ultra Low 20 nA (typical) Quiescent Current
• Ultra Low Shutdown Supply Current: 0.1 nA (typical)
• 200 mA Output Current Capability for VR ≤ 3.5V
• 100 mA Output Current Capability for VR 3.5V
• Input Operating Voltage Range: 2.5V to 5.5V
• Standard Output Voltages (VR):
- 1.2V, 1.5V, 1.8V, 2.0V, 2.5V, 3.0V, 3.3V, 4.2V
• Low Dropout Voltage: 450 mV Maximum at
200 mA
• Stable with 1.0 µF Ceramic Output Capacitor
• Overcurrent Protection
• Space-Saving, 8-Lead Plastic 2 x 2 VDFN
Applications
• Energy Harvesting
• Long Life Battery-Powered Applications
• Smart Cards
• Ultra Low Consumption “Green” Products
• Portable Electronics
Description
The MCP1710 is a 200 mA for VR ≤ 3.5V, 100 mA for
VR 3.5V, Low Dropout (LDO) linear regulator that
provides high-current and low-output voltages, while
maintaining an ultra low 20 nA of quiescent current
during device operation. In addition, the MCP1710 can
be shut down for an even lower 0.1 nA (typical) supply
current draw. The MCP1710 comes in eight standard,
fixed output voltage versions: 1.2V, 1.5V, 1.8V, 2V,
2.5V, 3V, 3.3V and 4.2V. The 200 mA output current
capability, combined with the low-output voltage
capability, make the MCP1710 a good choice for new
ultra long life LDO applications that have high-current
demands, but require ultra low-power consumption
during Sleep states.
The MCP1710 is stable using ceramic output
capacitors that inherently provide lower output noise,
and reduce the size and cost of the entire regulator
solution. Only 1 µF (2.2 µF recommended) of output
capacitance is needed to stabilize the LDO.
The MCP1710 device’s ultra low quiescent and
shutdown current allows it to be paired with other ultra
low-current draw devices, such as Microchip’s XLP
technology devices, for a complete ultra low-power
solution.
Package Type
MCP1710
2x2 VDFN*
GND 1
8 SHDN
VOUT 2 EP 7 VIN
NC 3 9 6 FB
NC 4
5 NC
* Includes Exposed Thermal Pad (EP); see Table 3-1.
2012-2015 Microchip Technology Inc.
DS20005158D-page 1
1 page  
MCP1710
2.0 TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, COUT = 2.2 µF Ceramic (X7R), CIN = 2.2 µF Ceramic (X7R), IOUT = 1 mA,
Temperature = +25°C, VIN = VR + 0.8V, SHDN = 1 M pull-up to VIN.
1.240
1.235
1.230
IOUT = 0.1 mA
TJ = -40°C
1.225
1.220
TJ = +25°C
1.215
1.210
1.205
1.200
TJ = +85°C
1.195
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Input Voltage (V)
FIGURE 2-1:
Output Voltage vs. Input
Voltage (VR = 1.2V).
1.205
1.200
1.195
VIN = 2.5V
TJ = +25°C
1.190
1.185
TJ = +85°C
1.180
1.175
TJ = -40°C
1.170
0
50 100 150
Load Current (mA)
200
FIGURE 2-4:
Output Voltage vs. Load
Current (VR = 1.2V).
2.510
2.508
2.506
IOUT = 0.1 mA
TJ = +25°C
2.504
2.502
2.500
2.498
TJ = -40°C
TJ = +85°C
2.496
2.494
2.5 3.0 3.5 4.0 4.5 5.0
Input Voltage (V)
5.5
FIGURE 2-2:
Output Voltage vs. Input
Voltage (VR = 2.5V).
2.5025
2.5000
TJ = +85°C
VIN = 3.3V
2.4975
2.4950
TJ = +25°C TJ = -40°C
2.4925
2.4900
0
20 40 60 80
Load Current (mA)
100
FIGURE 2-5:
Output Voltage vs. Load
Current (VR = 2.5V).
4.252
4.248 IOUT = 0.1 mA
4.244
TJ = -40°C
4.240
4.236
TJ = +25°C
TJ = +85°C
4.232
4.50
4.75 5.00 5.25
Input Voltage (V)
5.50
FIGURE 2-3:
Output Voltage vs. Input
Voltage (VR = 4.2V).
4.25
4.24
VIN = 4.15V
4.23
4.22
4.21
TJ = +25°C
TJ = +85°C
TJ = -40°C
4.20
4.19
0
20 40 60 80
Load Current (mA)
100
FIGURE 2-6:
Output Voltage vs. Load
Current (VR = 4.2V).
2012-2015 Microchip Technology Inc.
DS20005158D-page 5
5 Page 
MCP1710
3.0 PIN DESCRIPTION
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
MCP1710
VDFN
PIN FUNCTION TABLE
Name
Description
1
2
3, 4, 5
6
7
8
9
GND
VOUT
NC
FB
VIN
SHDN
EP
Ground
Regulated Output Voltage
Not Connected pins (should either be left floated or connected to ground)
Output Voltage Feedback Input
Input Voltage Supply
Shutdown Control Input (active-low)
Exposed Thermal Pad, Connected to GND
3.1 Ground Pin (GND)
For optimal noise and Power Supply Rejection Ratio
(PSRR) performance, the GND pin of the LDO should
be tied to an electrically quiet circuit ground. This will
help the LDO Power Supply Rejection Ratio and noise
performance. The GND pin of the LDO only conducts
the ground current, so a heavy trace is not required.
For applications that have switching or noisy inputs, tie
the GND pin to the return of the output capacitor.
Ground planes help lower the inductance and voltage
spikes caused by fast transient load currents.
3.2 Regulated Output Voltage Pin
(VOUT)
The VOUT pin is the regulated output voltage of the
LDO. A minimum output capacitance of 1.0 µF is
required for LDO stability. The MCP1710 is stable
with ceramic, tantalum and aluminum-electrolytic
capacitors. See Section 4.2 “Output Capacitor” for
output capacitor selection guidance.
3.3 Feedback Pin (FB)
The output voltage is connected to the FB input. This
sets the output voltage regulation value.
3.4 Input Voltage Supply Pin (VIN)
Connect the unregulated or regulated input voltage
source to VIN. If the input voltage source is located
several inches away from the LDO, or the input source
is a battery, it is recommended that an input capacitor
be used. A typical input capacitance value of 1 µF to
10 µF should be sufficient for most applications (2.2 µF,
typical). The type of capacitor used can be ceramic,
tantalum, or aluminum-electrolytic. The low-ESR
characteristics of the ceramic capacitor will yield better
noise and PSRR performance at high frequency.
3.5 Shutdown Control Input (SHDN)
The SHDN input is used to turn the LDO output voltage
on and off. When the SHDN input is at a logic high
level, the LDO output voltage is enabled. When the
SHDN input is pulled to a logic low level, the LDO
output voltage is disabled. When the SHDN input is
pulled low, the LDO enters a low quiescent current
shutdown state, where the typical quiescent current is
0.1 nA.
3.6 Exposed Thermal Pad (EP)
The VDFN-8 package has an exposed thermal pad on
the bottom of the package. The exposed thermal pad
gives the device better thermal characteristics by
providing a good thermal path to either the Printed
Circuit Board (PCB), or heat sink, to remove heat from
the device. The exposed pad of the package is at
ground potential.
2012-2015 Microchip Technology Inc.
DS20005158D-page 11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet MCP1710.PDF ] | |
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