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MCP2021A 데이터시트 PDF




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부품번호 MCP2021A 기능
기능 LIN Transceiver
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MCP2021A 데이터시트, 핀배열, 회로
MCP2021A/2A
LIN Transceiver with Voltage Regulator
Features:
• The MCP2021A/2A are compliant with LIN Bus
Specifications Version 1.3, 2.1 and with SAE
J2602-2
• Support Baud Rates up to 20 kBaud
• 43V Load Dump Protected
• Maximum Continuous Input Voltage: 30V
• Wide LIN-Compliant Supply Voltage: 6.0 – 18.0V
• Extended Temperature Range: -40 to +125°C
• Interface to PIC® MCU EUSART and Standard
USARTs
• Wake-Up on LIN Bus Activity or Local Wake Input
• Local Interconnect Network (LIN) Bus Pin:
- Internal Pull-Up Termination Resistor and
Diode for Slave Node
- Protected Against VBAT Shorts
- Protected Against Loss of Ground
- High-Current Drive
• TXD and LIN Bus Dominant Time-Out Function
• Two Low-Power Modes:
- Transmitter Off: 90 µA (typical)
- Power Down: 4.5 µA (typical)
• Output Indicating Internal Reset State (POR or
Sleep Wake)
• MCP2021A/2A On-Chip Voltage Regulator:
- Output Voltage of 5.0V or 3.3V
at 70 mA Capability with Tolerances of ±3%
Over the Temperature Range
- Internal Short Circuit Current Limit
- External Components Limited to Filter
Capacitor and Load Capacitor
• Automatic Thermal Shutdown
• High Electromagnetic Immunity (EMI), Low
Electromagnetic Emission (EME)
• Robust ESD Performance: ±15 kV for LBUS and
VBB pin (IEC61000-4-2)
• Transient Protection for LBUS and VBB Pins in
Automotive Environment (ISO7637)
• Meets Stringent Automotive Design
Requirements, including “OEM Hardware
Requirements for LIN, CAN and FlexRay
Interfaces in Automotive Applications”, Version
1.2, March 2011
• Multiple Package Options, including Small
4x4 mm DFN Package
Description:
The MCP2021A/2A provide a bidirectional, half-duplex
communication physical interface to meet the LIN bus
specification Revision 2.1 and SAE J2602-2. The
devices incorporate a voltage regulator with 5V or 3.3V
at 70 mA regulated power supply output. The devices
have been designed to meet the stringent quiescent
current requirements of the automotive industry and
will survive +43V load dump transients and double
battery jumps.
Package Types
RXD
CS/LWAKE
VREG
TXD
MCP2021A
PDIP, SOIC
18
27
36
45
FAULT/TXE
VBB
LBUS
VSS
MCP2021A
4x4 DFN
RXD 1
CS/LWAKE 2
VREG 3
TXD 4
8 FAULT/TXE
EP 7 VBB
9 6 LBUS
5 VSS
MCP2022A
PDIP, SOIC, TSSOP
RXD
CS/LWAKE
VREG
TXD
RESET
NC
NC
1
2
3
4
5
6
7
14 FAULT/TXE
13 VBB
12 LBUS
11 VSS
10 NC
9 NC
8 NC
* Includes Exposed Thermal Pad (EP), see Table 1-2.
2012-2014 Microchip Technology Inc.
DS20002298C-page 1




MCP2021A pdf, 반도체, 판매, 대치품
MCP2021A/2A
1.1.1 POWER-ON RESET MODE
Upon application of VBB or whenever the voltage on
VBB is below the threshold of regulator turn-off voltage
VOFF (typically 4.50V), the device enters Power-On
Reset (POR) mode. During this mode, the device
maintains the digital section in a Reset mode and waits
until the voltage on the VBB pin rises above the
threshold of regulator turn-on voltage VON (typically
5.75V) to enter Ready mode. In Power-On Reset
mode, the LIN physical layer and voltage regulator are
disabled and the RESET output (MCP2022A only) is
forced to low.
1.1.2 READY MODE
The device enters Ready mode from POR mode after
the voltage on VBB rises above the threshold of
regulator turn-on voltage VON or from Power-Down
mode when a remote or local wake-up event happens.
Upon entering Ready mode, the voltage regulator and
the receiver section of the transceiver are powered up.
The transmitter remains in an off state. The device is
ready to receive data but not to transmit. In order to
minimize the power consumption, the regulator
operates in a reduced-power mode. It has a lower
GBW product and it is thus slower. However, the 70 mA
drive capability is unchanged.
The device stays in Ready mode until the output of the
voltage regulator has stabilized and the CS/LWAKE pin
is high (‘1’).
1.1.3 OPERATION MODE
If VREG is OK (VREG > 0.8 VREG_NORM) and the
CS/LWAKE, FAULT/TXE and TXD pins are high, the
part enters Operation mode from either Ready or
Transmitter Off mode.
In this mode, all internal modules are operational. The
internal pull-up resistor between LBUS and VBB is
connected only in this mode.
The device goes into Power-Down mode at the falling
edge on CS/LWAKE or into Transmitter Off mode at the
falling edge on FAULT/TXE while CS/LWAKE stays
high.
1.1.4 TRANSMITTER OFF MODE
In Transmitter Off mode, the receiver is enabled but the
LBUS transmitter is off. It is a lower power mode.
In order to minimize power consumption, the regulator
operates in a reduced-power mode. It has a lower
GBW product and it is thus slower. However, the 70 mA
drive capability is unchanged.
The transmitter may be re-enabled whenever the
FAULT/TXE signal returns high, by removing the
internal fault condition and by driving FAULT/TXE high.
The transmitter will not be enabled even if the
FAULT/TXE pin is brought high externally, when the
internal fault is still present. However, externally forcing
the FAULT/TXE high while the internal fault is still
present should be avoided, since this will induce high
current and power dissipation in the FAULT/TXE pin.
The transmitter is also turned off whenever the voltage
regulator is unstable or recovering from a fault. This
prevents unwanted disruption of the bus during times of
uncertain operation.
1.1.5 POWER-DOWN MODE
In Power-Down mode, the transceiver and the voltage
regulator are both off. Only the bus wake-up section
and the CS/LWAKE pin wake-up circuits are in
operation. This is the lowest power mode.
If any bus activity (e.g., a Break character) occurs
during Power-Down mode, the device will immediately
enter Ready mode and enable the voltage regulator.
Then, once the regulator output has stabilized
(approximately 0.3 ms to 1.2 ms), it goes into
Operation mode. Refer to Section 1.1.6 “Remote
Wake-Up”.
The part will also enter Ready mode from Power-Down
mode, followed by the Operation mode, if the
CS/LWAKE pin becomes active high (‘1’).
1.1.6 REMOTE WAKE-UP
The Remote Wake-Up sub-module observes the LBUS
in order to detect bus activity. In Power-Down mode,
normal LIN recessive/dominant threshold is disabled
and the LIN bus wake-up voltage threshold VWK(LBUS)
is used to detect bus activities. Bus activity is detected
when the voltage on the LBUS falls below the LIN bus
wake-up voltage threshold VWK(LBUS) (approximately
3.5V) for at least tBDB (a typical duration of 80 µs)
followed by a rising edge. Such a condition causes the
device to leave Power-Down mode.
DS20002298C-page 4
2012-2014 Microchip Technology Inc.

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MCP2021A 전자부품, 판매, 대치품
MCP2021A/2A
1.2.7
GROUND (VSS)
Ground pin.
1.2.8
LIN BUS (LBUS)
LIN Bus pin. LBUS is a bidirectional LIN bus interface
pin and is controlled by the signal TXD. It has an open
collector output with a current limitation. To reduce
electromagnetic emission, the slopes during signal
changes are controlled and the LBUS pin has
corner-rounding control for both falling and rising
edges.
The internal LIN receiver observes the activities on the
LIN bus and generates the output signal RXD that
follows the state of the LBUS. A 1st degree 160 kHz
low-pass input filter optimizes electromagnetic
immunity.
1.2.9
BATTERY POSITIVE SUPPLY
VOLTAGE (VBB)
Battery Positive Supply Voltage pin. An external diode
is connected in series to prevent the device from being
reversely powered (refer to Figure 1-7).
1.2.10
FAULT DETECT
OUTPUT/TRANSMITTER ENABLE
INPUT (FAULT/TXE)
Fault Detect Output/Transmitter Enable Input pin. The
output section is HV-tolerant open-drain (up to 30V).
The input section is identical to the TXD section (TTL
level, HV-compliant, adaptive pull-up). The internal
pull-up resistor may be too weak for some applications.
We recommend adding a 10 kexternal pull-up
resistor to ensure a logic high level. Its state is defined
as shown in Table 1-5. The device is placed in
Transmitter Off mode whenever this pin is low (‘0’),
either from an internal fault condition or by external
drive.
If CS/LWAKE is high (‘1’), the FAULT/TXE signals a
mismatch between the TXD input and the LBUS level.
This can be used to detect a bus contention. Since the
bus exhibits a propagation delay, the sampling of the
internal compare is debounced to eliminate false faults.
After the device wakes up, the FAULT/TXE indicates
what wakes the device if CS/LWAKE remains low (‘0’)
(refer to Table 1-5).
The FAULT/TXE pin sampled at a rate faster than every
10 µs.
TABLE 1-3: FAULT/TXE TRUTH TABLE
TXD RXD LINBUS
In Out
I/O
Thermal
Override
FAULT/TXE
External Driven
Input Output
Definition
LH
VBB
OFF
CS = 1
H L FAULT, TXD driven low, LBUS shorted to VBB (Note 1)
or LBUS/TXD permanent dominant detected and Trans-
mit time-out shutdown.
HH
VBB
OFF
H
H OK
L L GND
OFF
H
H OK
H L GND
OFF
H
H OK, data is being received from LBUS
xx
VBB
ON
H
L FAULT, Transceiver in thermal shutdown
xx
VBB
x
L x NO FAULT, the CPU is commanding the transceiver
to turn off the transmitter driver
CS = 0
xx
x
x
x L Wake-up from LIN bus activity
xx
x
x
x H Wake-up from POR
Legend: x = Don’t care
Note 1: The FAULT/TXE is valid after approximately 25 µs after the TXD falling edge. This is to eliminate false fault
reporting during bus propagation delays.
2012-2014 Microchip Technology Inc.
DS20002298C-page 7

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