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PDF MCP2050 Data sheet ( Hoja de datos )
| Número de pieza | MCP2050 | |
| Descripción | LIN Transceiver | |
| Fabricantes | Microchip | |
| Logotipo |  |
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MCP2050
LIN Transceiver with Voltage Regulator
Features:
• The MCP2050 is compliant with:
- LIN Bus Specifications Version 1.3, 2.1 and
with SAE J2602-2
• Support Baud Rates Up to 20 kBaud
• 43V Load Dump Protected
• Maximum Continuous Input Voltage of 30V
• Wide LIN Compliant Supply Voltage, 6.0-18.0V
• Extended Temperature Range: -40 to +125°C
• Interface to PIC® EUSART and Standard USARTs
• Wake-Up on LIN Bus Activity or Local Wake Input
• LIN Bus Pin
- Internal pull-up termination resistor and diode
for slave node
- Protected against VBAT shorts
- Protected against loss of ground
- High current drive
• TXD and LIN Bus Dominant Time-Out Function
• Two Low-Power Modes
- Transmitter Off mode: 90 µA (typical)
- Power Down mode: 4.5 µA (typical)
• Output Indicating Internal Reset State (POR or
Sleep Wake)
• MCP2050 On-Chip Voltage Regulator
- Output voltage of 5.0V or 3.3V with 70 mA
capability and tolerances of ±3% over
operating temperature range
- Internal short-circuit current limit
- Only external filter and load capacitors needed
• Programmable Windowed Watchdog Timer
(WWDT)
- External resistor programmable from 7 ms to
140 ms
- Disabled by connecting the WWDTSELECT
pin to VREG or let the pin float
• Ratiometric Output of VBAT Voltage Scaled to
VREG
• Automatic Thermal Shutdown
• High Electromagnetic Immunity (EMI), Low
Electromagnetic Emission (EME)
• Robust ESD Performance: ±15 kV for LBUS and
VBB pin (IEC61000-4-2)
• Transient Protection for LBUS and VBB Pins in
Automotive Environment (ISO7637)
• Meets Stringent Automotive Design Requirements
Including “OEM Hardware Requirements for LIN,
CAN and FlexRay Interfaces in Automotive
Applications”, Version 1.3, May 2012
• Multiple Package Options Including Small 5x5
QFN
Description:
The MCP2050 provides a bidirectional, half-duplex
communication physical interface to meet the LIN bus
specification Revision 2.1 and SAE J2602. The device
incorporates a voltage regulator with 5V or 3.3V 70 mA
regulated power supply output. The on-chip WWDT
allows users to adjust the size of the reset window by
using an external resistor. The ratiometric VBAT pin
scales down VBAT to the range of VREG so it can be
monitored by an A/D converter.
The device has been designed to meet the stringent
quiescent current requirements of the automotive
industry and will survive +43V load dump transients,
and double battery jumps.
MCP2050 family members:
- MCP2050-500, 14-pin, LIN driver with 5.0V
regulator
- MCP2050-330, 14-pin, LIN driver with 3.3V
regulator
- MCP2050-500, 20-pin QFN, LIN driver with
5.0V regulator
- MCP2050-330, 20-pin QFN, LIN driver with
3.3V regulator
2012-2014 Microchip Technology Inc.
DS20002299C-page 1
1 page  
MCP2050
.
TABLE 1-1: OVERVIEW OF OPERATIONAL MODES
State
PoR
Ready
Operation
Power-Down
Transmitter Off
Transmitter
Receiver
Internal
Wake Module
Voltage
Regulator
Watch Dog
Timer
Operation
Comments
Off Off
Off On
Off
Off
Off
Off Proceed to Ready mode after VBB>VON.
—
On On If CS/LWAKE high, then proceed to Operation Bus Off state
or Transmitter Off mode.
On On
Off
On
On If CS/LWAKE low level, then proceed to
Normal
Power-Down.
Operation
If FAULT/TXE low level, then Transmitter-Off mode
mode.
Off Off
On
Off Off On LIN bus rising edge or CS/LWAKE high Lowest-
Activity Detect
level, proceed to READY mode.
Power mode
Off On
Off
On
Off If CS/LWAKE low level, then proceed to
Bus Off state,
Power down.
Lower-Power
If FAULT/TXE high, then Operation mode.
mode
1.2 Windowed Watchdog Reset
The Watchdog Timer monitors for activity on the
Windowed Watchdog Timer Trigger input pin
WWDTTRIG. The WWDTTRIG pin is expected to be
strobed within a given time frame. When this time frame
has expired without an edge transition on the WWDTTRIG
pin, the WWDTRESET pin is driven active (low) to reset
the system. This feature is enabled by connecting a
resistor between the WWDTSELECT pin and VSS.
Monitoring is then done by requiring the host processor to
force a falling edge transition on the WWDTTRIG pin
within a predetermined time frame (TWD).
The start time of the trigger window is fixed at 50% of
the total watchdog period, after the last trigger. The
length of the window is determined by the value of the
resistor on pin WWDTSELECT. The Watchdog Timer is
disabled if WWDTSELECT is floating.
1.2.1 WWDT DURING INITIAL POWER-UP
The WWDTRESET is driven high after a power-on
reset. The Watchdog Timer begins counting at this
point, awaiting an edge on WWDTTRIG pin. Note that
there is no window enabled, yet. If no falling edge is
detected on the WWDTTRIG pin before the timer
expires, the WWDTRESET is pulse low and the timer
is restarted. When a trigger edge on the WWDTTRIG
pin is seen, the window is enabled and the timer is reset.
FIGURE 1-2:
WWDTRESET DURING INITIAL POWER-UP
Internal
reset
WWDTRESET
tPOWERUP
tWDRST
tPOWERUP
tWDRST
tPOWERUP
Figure 1-2 shows the behavior of the WWDTRESET
pin after a system reset with no trig at all. If no trig is
given during the power-up window, WWDTRESET is
reset low for the time tWDRST.
The power-up window length tPOWERUP duration is
determined by the value of the resistor connected
between pin WWDTSELECT and pin VSS, while the
reset pulse duration is about 150 μs.
Duration for tPOWERUP and tWDRST are:
• tPOWERUP = 0.8 ms x (RWWDTSELECT+1) typical
• tWDRST = 150 μs typical
• RWWDTSELECT is in kΩ
Once a trig is asserted, the power-up sequence “stops”
and the normal behavior begins.
2012-2014 Microchip Technology Inc.
DS20002299C-page 5
5 Page 
1.4 Fail-Safe Features
1.4.1 GENERAL FAIL-SAFE FEATURES
• An internal pull-down resistor on the CS/LWAKE
pin disables the transmitter if the pin is floating.
• An internal pull-up resistor on the TXD pin places
TXD in high, thus the LBUS is recessive if the TXD
pin is floating.
• High-Impedance and low leakage current on LBUS
during loss of power or ground.
• The current limit on LBUS protects the transceiver
from being damaged if the pin is shorted to VBB.
1.4.2 THERMAL PROTECTION
The thermal protection circuit monitors the die
temperature and is able to shut down the LIN
transmitter and voltage regulator.
There are three causes for a thermal overload. A thermal
shut down can be triggered by any one, or a combination
of, the following thermal overload conditions.
• Voltage regulator overload
• LIN bus output overload
• Increase in die temperature due to increase in
environment temperature
The recovery time from the thermal shutdown is equal
to adequate cooling time.
Driving the TXD and checking the RXD pin makes it
possible to determine whether there is a bus contention
(TXD = high, RXD = low) or a thermal overload condition
(TXD = low, RXD = high).
FIGURE 1-7:
THERMAL SHUTDOWN
STATE DIAGRAMS
Output
Overload
LIN bus
shorted
to VBB
Voltage
Regulator
Shutdown
Operation
Mode
Transmitter
Shutdown
Temp < SHUTDOWNTEMP Temp < SHUTDOWNTEMP
MCP2050
1.4.3
TXD/LBUS TIME-OUT TIMER
LIN bus can be driven to a dominant level either from
TXD pin or externally. An internal timer deactivates the
LBUS transmitter if a dominant status (low) on LIN bus
lasts longer than Bus Dominant Time-Out Time tTO(LIN)
(approximately 20 ms); at the same time, RXD output is
put in recessive (high), FAULT/TXE is also driven to low
and the internal LIN pull-up resistor is disconnected.
The timer is reset on any recessive LBUS status or POR
mode. The recessive status on LBUS can be caused
either by the bus being externally pulled up or by TXD
pin being returned high.
2012-2014 Microchip Technology Inc.
DS20002299C-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MCP2050.PDF ] | |
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