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PDF ML7204-003 Data sheet ( Hoja de datos )
| Número de pieza | ML7204-003 | |
| Descripción | VoIP CODEC | |
| Fabricantes | LAPIS | |
| Logotipo |  |
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ML7204-003
VoIP CODEC
FEDL7204-003-02
Issue Date: Oct 14, 2011
GENERAL DESCRIPTION
The ML7204-003 is a speech CODEC for VoIP. As a speech CODEC, this LSI allows selection of
G.729.A/G711 and supports the PLC (Packet Loss Concealment) function.
With an echo canceler that handles 32 ms-delay and FSK detection/generation, DTMF detection/generation, and
tone detection/generation functions, the ML7204-003 is the most suitable LSI for adding the VoIP function to
TAs and routers.
FEATURES
Power supply voltage
Digital power supply voltage (DVDD0, 1, 2): 3.0 to 3.6 V
Analog power supply voltage (AVDD):
3.0 to 3.6 V
Speech CODEC:
G.729.A (8 kbps)/G.711 (64 kbps) -law and A-law (supports individual setting for transmission and
reception)
Supports ITU-T G.711 Appendix 1 compliant PLC (Packet Loss Concealment) function
Supports the 2-channel processing function (for 3-way communication)
Built-in FIFO buffer (640 bytes) for transmission/reception data transfer
Allows selection of Frame/DMA (slave) interface
Provided with echo canceler for handling 32 ms delay and Range Controllers
DTMF detection
DTMF generation (the tone generation function enables generation of DTMF signals)
Tone detection:
2 types (1650 Hz and 2100 Hz: Detection frequency can be changed)
Tone generation:
2 types
FSK detection
FSK generation
Built-in 16-bit timer:
1 channel
Dial pulse detection function (secondary function of general-purpose I/O ports)
Dial pulse transmission function (secondary function of general-purpose I/O ports)
General-purpose I/O ports : Equipped with 7 ports (with some of them having secondary function allocation)
Two types of built-in linear PCM CODEC (CODEC_A and CODEC_B)
Analog interface
CODEC_A side: Incorporates one type each of input amplifier and output amplifier (10 k driving)
CODEC_B side: Incorporates one type each of input amplifier and output amplifier (10 k driving)
PCM interface coding format:
Allows selection of 16-bit linear/G.711 (64 kbps) -law or A-law
PCM serial transmission rate: 64 kHz to 2.048 MHz (fixed to 2.048 MHz for output)
PCM time slot assignment function (allows up to 2 slots for input and 1 slot for output individually)
When set to -law/A-law: Supports up to 32 slots (BCLK: 2.048 MHz)
When set to 16-bit linear: Supports up to 16 slots (BCLK: 2.048 MHz)
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1 page  
FEDL7204-003-02
ML7204-003
PIN DESCRIPTIONS
Pin
QFP64
1
2
3
4
5
Symbol
TST1
TST0
PCMO
PCMI
BCLK
I/O
I
I
O
I
I/O
6
SYNC
I/O
7
DVDD0
—
8 ACK0B/GPIOA[4] I/O
9 ACK1B/GPIOA[5] I/O
10
FR0B
(DMARQ0B)
O
11
FR1B
(DMARQ1B)
O
12 INTB/GPIOA[6] I/O
13 CSB I
14 RDB I
15 WRB I
16
DGND0
—
17 D0 I/O
18 D1 I/O
19 D2 I/O
20 D3 I/O
21 D4 I/O
22 D5 I/O
23 D6 I/O
24 D7 I/O
When
PDNB
= “0”
“0”
“0”
“Hi-z”
I
I
“L”
I
“L”
—
I
I
”H”
“H”
“H”
I
I
I
—
I
I
I
I
I
I
I
I
Description
Test control input 1: Normally, input “0”.
Test control input 0: Normally, input “0”.
PCM data output [Open drain output pin]
PCM data input
CLKSEL = ”0”
PCM shift clock input
CLKSEL = ”1”
PCM shift clock output
CLKSEL = ”0”
PCM synchronous signal 8 kHz input
CLKSEL = ”1”
PCM synchronous signal 8 kHz output
Digital power supply
Transmit buffer DMA access acknowledge signal input
(primary function)
General-purpose I/O port A[4] (secondary function) [5
V tolerant pin]
Receive buffer DMA access acknowledge signal input
(primary function)
General-purpose I/O port A [5] (secondary function) [5 V
tolerant pin]
FR0B:(FD_SEL = ”0”)
Transmit buffer frame signal output
DMARQ0B: (FD_SEL = ”1”)
Transmit buffer DMA access request signal output
FR1B: (FD_SEL = ”0”)
Receive buffer frame signal output
DMARQ1B: (FD_SEL = ”1”)
Receive buffer DMA access request signal output
Interrupt request output (primary function)
General-purpose I/O port A [6] (secondary function) [5 V
tolerant pin]
Chip select control input
Read control input
Write control input
Digital ground (0.0 V)
Data input-output
Data input-output
Data input-output
Data input-output
Data input-output
Data input-output
Data input-output
Data input-output
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5 Page 
FEDL7204-003-02
ML7204-003
AC Characteristics in Speech CODEC = G.711 (-law) Mode
(AVDD = 3.0 to 3.6V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2
= 0.0 V, Ta = –20 to 60C unless otherwise specified)
Parameter
Symbol
Condition
Frequency (Hz)
Level (dBm0)
Min. Typ. Max. Unit
LT1 0 to 60
25 — —
dB
LT2 300 to 3000
–0.15 — 0.20
dB
Transmit frequency
characteristics
LT3
LT4
1020
3300
0
Reference
–0.15 — 0.80
—
dB
LT5 3400
0
— 0.80
dB
LT6 3968.75
13 — —
dB
LR2 0 to 3000
–0.15 — 0.20
dB
Receive frequency
characteristics
LR3
LR4
LR5
1020
3300
3400
Reference
—
0
–0.15 — 0.80
dB
0
— 0.80
dB
LR6 3968.75
13 — —
dB
SDT1
3 35 — — dBp
Transmit
SDT2
0 35 — — dBp
signal-to-noise ratio
SDT3
1020
–30 35 — — dBp
(*1) SDT4
–40 28 — — dBp
SDT5
–45 23 — — dBp
SDR1
3 35 — — dBp
Receive
SDR2
0 35 — — dBp
signal-to-noise ratio
SDR3
1020
–30 35 — — dBp
(*1) SDR4
–40 28 — — dBp
SDR5
–45 23 — — dBp
GTT1
3
–0.2 —
0.2
dB
Transmit inter-level
loss errors
GTT2
GTT3
GTT4
1020
–10
Reference
—
–40
–0.2 —
0.2
dB
–50
–0.6 —
0.6
dB
GTT5
–55
–1.2 —
1.2
dB
GTR1
3
–0.2 —
0.2
dB
Receive inter-level
loss errors
GTR2
GTR3
GTR4
1020
–10
Reference
—
–40
–0.2 —
0.2
dB
–50
–0.6 —
0.6
dB
GTR5
–55
–1.2 —
1.2
dB
Idle channel noise
(*1)
NIDLT
NIDLR
—
—
Analog input =
AVREF
PCMI = ”1”
—
—
— –70 dBm0p
— –70 dBm0p
Transmit absolute
level (*2)
AVT
1020
0 0.285 0.320 0.359 Vrms
Receive absolute level
(*2)
AVR
1020
0 0.285 0.320 0.359 Vrms
*1 P-message weighted filter used
*2 0.320 Vrms = 0 dBm0 = –7.7 dBm (600)
11/214
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ML7204-003.PDF ] | |
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