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부품번호 | 6V49205B 기능 |
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기능 | Freescale P10XX and P20XX System Clock w/Selectable DDR Frequency | ||
제조업체 | IDT | ||
로고 | |||
전체 16 페이지수
Freescale P10XX and P20XX System Clock
w/Selectable DDR Frequency
6V49205B
DATASHEET
General Description
The 6V49205B is a main clock for Freescale P10xx and
P20xx-based systems. It has a selectable System CCB clock
and 2 DDRCLK speeds – 100M or 66.66M. The 6V49205B
also provides LP-HCSL PCIe outputs for low power and
reduced board space.
Output Features
• 1 - Sys_CCB 3.3V LVCMOS output @ 100M/83.33M/
80M/66.66M
• 1 - DDRCLK 3.3V LVCMOS output @ 100M or 66.66M 1
• 1 - 125M 3.3V LVCMOS output
• 6 - LP-HCSL PCIe pairs selectable @ 100M or 125M
• 6 - 25MHz 3.3V LVCMOS outputs
• 2 - 2.048M 3.3V LVCMOS outputs
• 2 - USB 3.3V LVCMOS outputs @12M or 24M
Key Specifications
• PCIe Gen1-2-3 compliant
• <3p rms phase noise on REF outputs
Recommended Application
System Clock for Freescale P10xx and P20xx-based designs
Features
• Replaces 11 crystals, 2 oscillators and 3 clock generators;
lowers cost, power and area
• Integrated terminations on LP-HCSL PCIe outputs;
eliminate 24 resistors, saving 41mm2 of board area
• Industrial temperature range operation; supports
demanding environmental conditions
• Advanced 3.3V CMOS process; high-performance,
low-power
• Supports independent spread spectrum on
Sys_CCB/DDRCLK and PCIe outputs
• Available in space-saving 7x7mm 48-pin VFQFPN with
0.5mm pad pitch; reduced board space without the need for
fine-pitch assembly techniques
Block Diagram
SCLK
SDATA
^FS0
^FS1
^SEL100#_66
^SELPCIE125#_100
X1
25MHz
Crystal
X2
Control
Logic
Crystal
Oscillator
PLL1
(SS)
PLL4
(SS)
PLL3
(non-
SS)
PLL2
(non-
SS)
100MHz
GND
Sys_CCB
DDRCLK
PCIe_L(5:0)
USB_CLK(2:1)
2.048M(1:0)
125M
REF(5:0)
Note 1: For DDR Clock: Processor core and I/O supply rails must be ramped with VDD3P3 or earlier. Clock signal will be
clamped LOW and output clock will be 100MHz if this is not followed (see diagram below).
VDD3P3
DDRCLK
R40 10K
R39 10K
6V49205B REVISION R 11/23/16 1 ©2016 Integrated Device Technology, Inc.
6V49205B DATASHEET
Table 1: PCIEX Spread Table (selectable via SMBUS)
SELPCIE125#_100
B6b4
B0b4
B0b3
Spread %
0 (125MHz)
x
x No Spread
1 (100MHz)
0
0 No Spread (default)
1 (100MHz)
0
1 Down -0.5%
1 (100MHz)
1
0 Down -0.75%
1 (100MHz)
1
1 No Spread
*Once in spread mode, do not return to non spread without reset
Table 2: Sys_CCB and DDR Spread Table (selectable via SMBUS)
B0b7
0
0
0
0
1
1
1
1
B0b6
0
0
1
1
0
0
1
1
B0b5
0
1
0
1
0
1
0
1
Spread %
No Spread (default)
Down -0.5%
Down -0.75%
Down -0.25%
Down -1%
Down -1.25%
Down -1.5%
Down -2%
Table 3: Sys_CCB Frequency Select Table (Latched and selectable via SMBUS)
FS1 /
B4b3
0
0
0
0
FS0 /
B4b2
0
0
1
1
Sys_CCB (MHz)
66.66
100
80
83.33
Table 4: PCI Express Amplitude Control
B6b7
0
0
1
1
B6b6
0
1
0
1
PCIe Amplitude
700mV
800mV
900mV
1000mV
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/SELECTABLE DDR FREQUENCY
4
REVISION R 11/23/16
4페이지 6V49205B DATASHEET
Electrical Characteristics - DDR Clock
PARAMETER
DDR Clock Frequency
Synthesis error
Output High Voltage
Output Low Voltage
Slew Rate
VDDO = 3.3V
Duty Cycle
Jitter, Peak period jitter
Phase Noise
AC Input Swing Limits @ 3.3V
OVDD
Spread Spectrum Modulation
Frequency
SYMBOL
fDDR66.66
fDDR100
ppmSSof f
ppmSSon
VOH
VOL
tSLEW00
tSLEW01
tSLEW10
tSLEW11
dt1
tjpeak
tphasenoise
CONDITIONS
SEL100#_66 = 1, VT = OVDD/2 V
SEL100#_66 = 0, VT = OVDD/2 V
Spread off
Spread on
VOH at the selected operating frequency
VOL at the selected operating frequency
'00' = Hi-Z
'01' Slow Slew Rate (Averaging on)
'10' Fast Slew Rate (Averaging on)
'11' Fastest Slew Rate (Averaging on)
VT = OVDD/2 V
VT = OVDD/2 V
-56dBc
MIN TYP MAX
66.666
100.00
0
+/-150
2.4
0.4
Hi-Z
1.1 1.6 2.3
1.6 2.3 3.2
1.8 2.7 3.7
40 51.4 60
±96 ±150
10 500
VAC
This is the difference between VOL and
VOH at the selected operating frequency.
1.9
3.4
fSSMOD
Triangular Modulation
30 32.3 60
Electrical Characteristics - Sys_CCB
PARAMETER
Clock Frequency
Synthesis error
Output High Voltage
Output Low Voltage
Slew Rate
VDDO = 3.3V
Duty Cycle
Jitter, Peak period jitter
Phase Noise
AC Input Swing Limits @ 3.3V
OVDD
Spread Spectrum Modulation
Frequency
SYMBOL
fSy s_CCB
ppmSSof f
ppmSSon
VOH
VOL
tSLEW00
tSLEW01
tSLEW10
tSLEW11
dt1
tjpeak
tphasenoise
CONDITIONS
FS(1:0) = 00, VT = OVDD/2 V
FS(1:0) = 01, VT = OVDD/2 V
FS(1:0) = 10, VT = OVDD/2 V
FS(1:0) = 11, VT = OVDD/2 V
Spread off
Spread on
VOH at the selected operating frequency
VOL at the selected operating frequency
'00' = Hi-Z
'01' Slow Slew Rate (Averaging on)
'10' Fast Slew Rate (Averaging on)
'11' Fastest Slew Rate (Averaging on)
VT = OVDD/2 V
VT = OVDD/2 V, SSC < 0.75%
-56dBc
MIN TYP MAX
66.666
100.00
80.00
83.333
0
+/-150
2.4
0.4
Hi-Z
0.8 1.4 2.1
0.9 1.6 2.5
1.1 1.9 3.1
40 51.4 60
±116
±150
10 500
VAC
This is the difference between VOL and
VOH at the selected operating frequency.
1.9
fSSMOD
Triangular Modulation
0 31.5 60
Electrical Characteristics - 125M
PARAMETER
Clock frequency
Synthesis error
Output High Voltage
Output Low Voltage
Rise/Fall time
VDDO = 3.3V
Duty Cycle
Jitter, Peak period jitter
SYMBOL
f125M
ppm
VOH
VOL
tRF125M3.3V
dt1
tjpeak
CONDITIONS
VT = OVDD/2 V
VOH at the selected operating frequency
VOL at the selected operating frequency
Measured between 0.6V and 2.7V
VT = OVDD/2 V
VT = OVDD/2 V
MIN TYP MAX
125.00
0
2.2
0.5
0.7 1
47 52 53
±150
UNITS
MHz
MHz
ppm
ppm
V
V
V/ns
V/ns
V/ns
V/ns
%
ps
kHz
NOTES
2,3,6
2,3,6
1,2,5
1,2,5
1
1
1,3,8
1,3,8
1,3,8
1,6
1,6
1,7
V1
kHz
UNITS
MHz
MHz
MHz
MHz
ppm
ppm
V
V
V/ns
V/ns
V/ns
V/ns
%
ps
kHz
NOTES
2,3,6
2,3,6
2,3,6
2,3,6
1,2,5
1,2,5
1
1
1,3,8
1,3,8
1,3,8
1,6
1
1,7
V1
kHz
UNITS
ns
ppm
V
V
ns
%
ps
NOTES
2,3,6
1,2,5
1
1
1,3
1
1
REVISION R 11/23/16
7 FREESCALE P10XX AND P20XX SYSTEM CLOCK W/SELECTABLE DDR FREQUENCY
7페이지 | |||
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부품번호 | 상세설명 및 기능 | 제조사 |
6V49205B | Freescale P10XX and P20XX System Clock w/Selectable DDR Frequency | IDT |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |