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PDF 8T73S208B-01 Data sheet ( Hoja de datos )
| Número de pieza | 8T73S208B-01 | |
| Descripción | LVPECL Clock Divider and Fanout Buffer | |
| Fabricantes | IDT | |
| Logotipo |  |
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2.5 V, 3.3 V Differential LVPECL Clock
Divider and Fanout Buffer
8T73S208B-01
Datasheet
General Description
The 8T73S208B-01 is a high-performance differential LVPECL clock
divider and fanout buffer. The device is designed for the frequency
division and signal fanout of high-frequency, low phase-noise clocks.
The 8T73S208B-01 is characterized to operate from a 2.5V and 3.3V
power supply. Guaranteed output-to-output and part-to-part skew
characteristics make the 8T73S208B-01 ideal for those clock
distribution applications demanding well-defined performance and
repeatability. The integrated input termination resistors make
interfacing to the reference source easy and reduce passive
component count. Each output can be individually enabled or
disabled in the high-impedance state controlled by a I2C register. On
power-up, all outputs are disabled.
Features
• One differential input reference clock
• Differential pair can accept the following differential input
levels: LVDS, LVPECL, CML
• Integrated input termination resistors
• Eight LVPECL outputs
• Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8
• Maximum input clock frequency: 1GHz
• LVCMOS interface levels for the control inputs
• Individual output enable/disabled by I2C interface
• Power-up state: all outputs disabled
• Output skew: 60ps (maximum)
• Output rise/fall times: 350ps (maximum)
• Low additive phase jitter, RMS: 182fs (typical)
• Full 2.5V and 3.3V supply voltages
• Lead-free (RoHS 6) 32-Lead VFQFN packaging
• -40°C to 85°C ambient operating temperature
Block Diagram
IN
nIN
50
fREF
÷1, ÷2,
÷4, ÷8
50
VT
FSEL[1:0]
Pulldown (2)
2
SDA
SCL
Pullup
Pullup
I2C 8
ADR[1:0]
Pulldown (2)
2
Pin Assignment
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
ADR1
VEE
Q0
nQ0
Q1
nQ1
VEE
VCCO
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4 21
5 20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
FSEL0
VEE
nQ7
Q7
nQ6
Q6
VEE
VCCO
Q7
nQ7
5mm x 5mm, 32-pin VFQFN
©2016 Integrated Device Technology, Inc.
1
April 28, 2016
1 page  
8T73S208B-01 Datasheet
Table 4B. LVCMOS/LVTTL Input DC Characteristics, VCC = VCCO = 2.5V ± 5% or 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FSEL[1:0], ADR[1:0]
VCC = 3.3V ± 5%
2.2
VCC + 0.3V
V
VIH
Input
SCL, SDA
High Voltage1
VCC = 3.3V ± 5%
FSEL[1:0], ADR[1:0]
VCC = 2.5V ± 5%
SCL, SDA
VCC = 2.5V ± 5%
FSEL[1:0], ADR[1:0]
VCC = 3.3V ± 5%
VIL
Input
SCL, SDA
Low Voltage1 FSEL[1:0], ADR[1:0]
VCC = 3.3V ± 5%
VCC = 2.5V ± 5%
SCL, SDA
VCC = 2.5V ± 5%
IIH
Input
High Current
FSEL[1:0], ADR[1:0]
SCL, SDA
VCC = VIN = 2.625 or 3.465V
VCC = VIN = 2.625 or 3.465V
IIL
Input
Low Current
FSEL[1:0], ADR[1:0]
SCL, SDA
VCC = 2.625 or 3.465V, VIN = 0V
VCC = 2.625 or 3.465V, VIN = 0V
NOTE 1: VIL should not be lower than -0.3V and VIH should not be higher than VCC + 0.3V.
2.4
1.7
1.9
-0.3
-0.3
-0.3
-0.3
-10
-150
VCC + 0.3V
VCC + 0.3V
VCC + 0.3V
0.8
0.8
0.7
0.5
150
10
V
V
V
V
V
V
V
µA
µA
µA
µA
Table 4C. Differential Input DC Characteristics, VCC = VCCO = 2.5V ± 5% or 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIN
VCMR
Input Voltage Swing1 IN, nIN
Common Mode Input Voltage1, 2
0.15
1.2
1.2
VCC – (VIN/2)
V
V
VDIFF_IN Differential Input Voltage Swing
0.3 2.4 V
RIN
Input Resistance
IN, nIN
IN, nIN to VT
40 50
60
RIN_DIFF
Differential
Input Resistance
IN, nIN
IN to nIN, VT = Open
80 100 120
NOTE 1: VIL should not be less than -0.3V and VIH should not be greater than VCC
NOTE 2: Common Mode Input Voltage is defined as the cross point.
©2016 Integrated Device Technology, Inc.
5
April 28, 2016
5 Page 
8T73S208B-01 Datasheet
Applications Information
3.3V Differential Input with Built-In 50 Termination Interface
The IN /nIN with built-in 50 terminations accept LVDS, LVPECL,
CML and other differential signals. Both signals must meet the VIN
and VCMR input requirements. Figures 4A to 4C show interface
examples for the IN/nIN input with built-in 50 terminations driven by
the most common driver types. The input interfaces suggested here
are examples only. If the driver is from another vendor, use their
termination recommendation. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
Figure 4A. IN/nIN Input with Built-In 50
Driven by an LVDS Driver
Figure 4B. IN/nIN Input with Built-In 50
Driven by an LVPECL Driver
Figure 4C. IN/nIN Input with Built-In 50
Driven by a CML Driver
©2016 Integrated Device Technology, Inc.
11
April 28, 2016
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet 8T73S208B-01.PDF ] | |
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