9FG1901H Datasheet PDF - IDT
| Part Number | 9FG1901H | |
| Description | Frequency Generator | |
| Manufacturers | IDT | |
| Logo |  |
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Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
DATASHEET
9FG1901H
Description
Features/Benefits
The 9FG1901H follows the Intel DB1900G Differential Buffer
Specification. This buffer provides 19 output clocks for CPU Host
Bus, PCI-Express, or Fully Buffered DIMM applications. The outputs
are configured with two groups. Both groups, DIF_(16:0) and
DIF_(18:17) can be equal to or have a gear ratio to the input clock.
A differential CPU clock from a CK410B+ main clock generator,
such as the ICS932S421, drives the ICS9FG1901. The 9FG1901H
can provide outputs up to 400MHz.
•
•
•
•
•
•
•
Power up default is all outputs in 1:1 mode
DIF_(16:0) can be “gear-shifted” from the input CPU Host
Clock
DIF_(18:17) can be “gear-shifted” from the input CPU Host
Clock
Spread spectrum compatible
Supports output clock frequencies up to 400 MHz
8 Selectable SMBus addresses
SMBus address determines PLL or Bypass mode
Key Specifications
• VDDA controlled power down mode
• DIF output cycle-to-cycle jitter < 50ps
• DIF output-to-output skew across all outputs in 1:1 mode < 150ps
Functional Block Diagram
OE_17_18#
OE(16:5)#, 13
OE_01234#
CLK_IN
CLK_IN#
HIGH_BW#
FS_A_410
SMB_A0
SMB_A1
SMB_A2_PLLBYP#
SMBDAT
SMBCLK
SPREAD
COMPATIBLE
PLL
SPREAD
COMPATIBLE
PLL
CONTROL
LOGIC
GEAR
SHIFT
LOGIC
STOP
LOGIC
2
DIF(18:17)
GEAR
SHIFT
LOGIC
STOP
LOGIC
17
DIF(16:0)
IREF
IDTTM Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
1
1386A - 02/02/10
|
| |
 
9FG1901H
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
9FG1901 Programmable Gear Ratios
SMBus
Byte 0
Input Output Gear Ratio
(m) (n)
(n/m)
Input (CPU FSB) and Output
Frequencies (MHz)
200.0 266.7 320.0 333.3 400.0
00000 3
1
0.333 66.7 88.9 106.7 111.1 133.3
00001 5
2
0.400 80.0 106.7 128.0 133.3 160.0
0 0 0 1 0 12
5
0.417 83.3 111.1 133.3 138.9 166.7
00011 2
1
0.500 100.0 133.3 160.0 166.7 200.0
00100 5
3
0.600 120.0 160.0 192.0 200.0 240.0
00101 8
5
0.625 125.0 166.7 200.0 208.3 250.0
00110 3
2
0.667 133.3 177.8 213.3 222.2 266.7
00111 4
3
0.750 150.0 200.0 240.0 250.0 300.0
01000 6
5
0.833 166.7 222.2 266.7 277.8 333.3
01001 1
1
1.000 200.0 266.7 320.0 333.3 400.0
01010 5
6
1.200 240.0 320.0 384.0 400.0 NA
01011 4
5
1.250 250.0 333.3 400.0 NA NA
01100 3
4
1.333 266.7 355.6 NA
NA NA
01101 2
3
1.500 300.0 400.0 NA
NA NA
01110 3
5
1.667 333.3 NA NA NA NA
01111 1
2
2.000 400.0 NA NA NA NA
CLK IN (CPU FSB) Frequency (MHz)
100 133.33 160 166.67
10000 3
1
0.333
10001 5
2
0.400
NA 53.3 64.0 66.7
1 0 0 1 0 12
5
0.417
NA 55.6 66.7 69.4
10011 2
1
0.500 50.0 66.7 80.0 83.3
10100 5
3
0.600 60.0 80.0 96.0 100.0
10101 8
5
0.625 62.5 83.3 100.0 104.2
10110 3
2
0.667 66.7 88.9 106.7 111.1
10111 5
4
0.800 80.0 106.7 128.0 133.3
11000 6
5
0.833
NA 111.1 133.3 138.9
11001 1
1
1.000 100.0 133.3 160.0 166.7
11010 5
6
1.200 120.0 160.0 192.0 200.0
11011 4
5
1.250 125.0 166.7 200.0 208.3
11100 3
4
1.333 133.3 177.8 213.3 222.2
11101 2
3
1.500 150.0 200.0
11110 3
5
1.667 166.7 222.2 266.7 277.8
11111 1
2
2.000 200.0 266.7 320.0 333.3
Note: Lines in BOLD are Power-up defaults for FS_A_410 = 0 and 1 respectively.
Shaded areas are shown for reference only and device operation is not guaranteed
IDTTM Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
5
1386A - 02/02/10
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for 9FG1901H electronic component. |
| Information | Total 18 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ 9FG1901H.PDF Datasheet ] | |
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