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9FGU0441 데이터시트 PDF




IDT에서 제조한 전자 부품 9FGU0441은 전자 산업 및 응용 분야에서
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부품번호 9FGU0441 기능
기능 4 O/P 1.5V PCIe Gen1-2-3 Clock Generator
제조업체 IDT
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9FGU0441 데이터시트, 핀배열, 회로
4 O/P 1.5V PCIe Gen1-2-3 Clock Generator
w/Zo=100ohms
9FGU0441
DATASHEET
Description
The 9FGU0441 is a member of IDT's 1.5V Ultra-Low-Power
PCIe clock family with integrated output terminations
providing Zo=100. The device has 4 output enables for
clock management, 2 different spread spectrum levels in
addition to spread off and 2 selectable SMBus addresses.
Recommended Application
1.5V PCIe Gen1-2-3 clock generator
Output Features
4 - 100MHz Low-Power (LP) HCSL DIF pairs
w/Zo=100ohms
1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF phase jitter is PCIe Gen1-2-3 compliant
REF phase jitter is < 3.0ps RMS
Block Diagram
Features/Benefits
Direct connection to 100ohm transmission lines; saves 16
resistors compared to standard PCIe devices
39mW typical power consumption; reduced thermal
concerns
OE# pins; support DIF power management
Programmable Slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
DIF outputs blocked until PLL is locked; clean system
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
3.3V tolerant SMBus interface works with legacy controllers
Space saving 32-pin 5x5 mm VFQFPN; minimal board
space
XIN/CLKIN_25
X2
vOE(3:0)#
OSC
REF1.5
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
SS Capable PLL
DIF3
DIF2
DIF1
DIF0
9FGU0441 OCTOBER 18, 2016
1 ©2016 Integrated Device Technology, Inc.




9FGU0441 pdf, 반도체, 판매, 대치품
9FGU0441 DATASHEET
Test Loads
Low-Power HCSL Differential Output Test Load
5 inches
Rs
Zo=100ohm
Rs
Device
2pF 2pF
REF Output Test Load
Zo = 50 ohms
33
5pF
REF Output
Alternate Terminations
Driving LVDS
Rs
Device
Rs
Cc
Cc
3.3V
R7a
Zo
R8a
R7b
R8b
LVDS Clock
input
Driving LVDS inputs
Value
Receiver has Receiver does not
Component
termination have termination Note
R7a, R7b
10K ohm
140 ohm
R8a, R8b
5.6K ohm
75 ohm
Cc
0.1 uF
0.1 uF
Vcm
1.2 volts
1.2 volts
4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
4
OCTOBER 18, 2016

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9FGU0441 전자부품, 판매, 대치품
9FGU0441 DATASHEET
Electrical Characteristics–DIF Low-Power HCSL Outputs
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Slew rate
Slew rate matching
SYMBOL
Trf
ΔTrf
CONDITIONS
Scope averaging on fast setting
Scope averaging on slow setting
Slew rate matching, Scope averaging on
MIN TYP MAX UNITS NOTES
1.2 2.4 3.6 V/ns 1,2,3
0.8 1.7 2.5 V/ns 1,2,3
9 20 % 1,2,4
Voltage High
Voltage Low
VHIGH
VLOW
Statistical measurement on single-ended signal 600 750 850
using oscilloscope math function. (Scope
mV
averaging on)
-150 26 150
7
7
Max Voltage
Min Voltage
Vmax
Vmin
Measurement on single ended signal using
absolute value. (Scope averaging off)
763 1150
-300 22
mV
7
7
Vswing
Vswing
Scope averaging off
300 1448
mV 1,2,7
Crossing Voltage (abs) Vcross_abs
Scope averaging off
250 390 550 mV 1,5,7
Crossing Voltage (var)
Δ-Vcross
Scope averaging off
11 140 mV 1,6,7
1Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.
7 At default SMBus amplitude settings.
Electrical Characteristics–DIF Output Phase Jitter Parameters
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
tjphPCIeG1
Phase Jitter, PLL Mode
tjphPCIeG2
tjphPCIeG3
PCIe Gen 1
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3 Common Clock Architecture
(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
27.7
1.0
1.9
0.4
MAX
40
1.3
2.2
0.6
IND.
LIMIT
86
3
3.1
1
UNITS Notes
ps (p-p) 1,2,3,5
ps 1,2,3,5
(rms)
ps 1,2,3,5
(rms)
ps
(rms)
1,2,3,5
tjphPCIeG3SRn PCIe Gen 3 Separate Reference No Spread (SRnS)
S (PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
0.4 0.6 0.7
1 Guaranteed by design and characterization, not 100% tested in production.
2 See http://www.pcisig.com for complete specs
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4 Calculated from Intel-supplied Clock Jitter Tool
5 Applies to all differential outputs
ps
(rms) 1,2,3,5
OCTOBER 18, 2016
7 4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS

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부품번호상세설명 및 기능제조사
9FGU0441

4 O/P 1.5V PCIe Gen1-2-3 Clock Generator

IDT
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