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9FGV0631C 데이터시트 PDF




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부품번호 9FGV0631C 기능
기능 6-O/P 1.8V PCIe Gen 1-2-3 Clock Generator
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9FGV0631C 데이터시트, 핀배열, 회로
6-O/P 1.8V PCIe Gen 1-2-3 Clock Generator 9FGV0631C
DATASHEET
General Description
The 9FGV0631C is a member of IDT's SOC-Friendly 1.8V
Very-Low-Power PCIe clock family. The device has 6 output
enables for clock management, 2 different spread spectrum
levels in addition to spread off and 2 selectable SMBus
addresses.
Recommended Application
1.8V PCIe Gen 1-2-3 Clock Generator
Output Features
6 - 100MHz Low-Power (LP) HCSL DIF pairs
1 - 1.8V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF phase jitter is PCIe Gen1-2-3 Compliant
REF phase jitter is <1.5ps RMS
Block Diagram
Features/Benefits
LP-HCSL outputs; save 12 resistors compared to standard
PCIe devices
54mW typical power consumption; reduced thermal
concerns
Outputs can optionally be supplied from any voltage
between 1.05V and 1.8V; maximum power savings
OE# pins; support DIF power management
Programmable Slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
DIF outputs blocked until PLL is locked; clean system
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
3.3V tolerant SMBus interface works with legacy controllers
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
Space saving 40-pin 5x5 mm VFQFPN; minimal board
space
vOE(5:0)#
XIN/CLKIN_25
X2
OSC
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
SS Capable PLL
REF1.8
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9FGV0631C OCTOBER 18, 2016
1 ©2016 Integrated Device Technology, Inc.




9FGV0631C pdf, 반도체, 판매, 대치품
9FGV0631C DATASHEET
Test Loads
Low-Power Differential Output Test Load
Rs
Rs
5 inches
Zo=100 ohms
2pF 2pF
Alternate Differential Output Terminations
Rs Zo Units
33
27
100
85
Ohms
REF Output Test Load
Zo = 50 ohms
33
5pF
REF Output
Driving LVDS
Rs
Rs
Cc
Cc
3.3 Volts
R7a R7b
L4
R8a R8b
Driving LVDS inputs
Value
Receiver has Receiver does not
Component
termination have termination Note
R7a, R7b
10K ohm
140 ohm
R8a, R8b
5.6K ohm
75 ohm
Cc
0.1 uF
0.1 uF
Vcm
1.2 volts
1.2 volts
LVDS CLK
Input
6-O/P 1.8V PCIE GEN 1-2-3 CLOCK GENERATOR
4
OCTOBER 18, 2016

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9FGV0631C 전자부품, 판매, 대치품
9FGV0631C DATASHEET
Electrical Characteristics–DIF Low Power HCSL Outputs
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Slew rate
Slew rate matching
SYMBOL
Trf
ΔTrf
CONDITIONS
Scope averaging on fast setting
Scope averaging on slow setting
Slew rate matching, Scope averaging on
MIN TYP MAX UNITS NOTES
1.8 2.7 4.4 V/ns 1,2,3
1.4 2.1 3.4 V/ns 1,2,3
4 20 % 1,2,4
Voltage High
Voltage Low
VHIGH
VLOW
Statistical measurement on single-ended signal 660 793 850
using oscilloscope math function. (Scope
mV
averaging on)
-150 16 150
7
7
Max Voltage
Min Voltage
Vmax
Vmin
Measurement on single ended signal using
absolute value. (Scope averaging off)
831 1150 mV
-300 -95
7
7
Vswing
Vswing
Scope averaging off
300 1555
mV 1,2,7
Crossing Voltage (abs) Vcross_abs
Scope averaging off
250 429 550 mV 1,5,7
Crossing Voltage (var)
Δ-Vcross
Scope averaging off
12 140 mV 1,6,7
1Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the
average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting -Vcross to be smaller than Vcross absolute.
7 At default SMBus amplitude settings.
Electrical Characteristics–DIF Output Phase Jitter Parameters
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
tjphPCIeG1
Phase Jitter, PLL Mode4
tjphPCIeG2
tjphPCIeG3
PCIe Gen 1
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3 Common Clock Architecture
(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
25 35
0.9 1.1
1.6 1.9
0.36 0.5
tjphPCIeG3SRn PCIe Gen 3 Separate Reference No Spread (SRnS)
S (PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
0.36 0.5
1 Guaranteed by design and characterization, not 100% tested in production.
2 See http://www.pcisig.com for complete specs
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4 Applies to all differential outputs
IND.
LIMIT
86
3
3.1
1
UNITS
ps (p-p)
ps
(rms)
ps
(rms)
ps
(rms)
Notes
1,2,3
1,2,3
1,2,3
1,2,3
0.7
ps
(rms) 1,2,3
OCTOBER 18, 2016
7 6-O/P 1.8V PCIE GEN 1-2-3 CLOCK GENERATOR

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9FGV0631C

6-O/P 1.8V PCIe Gen 1-2-3 Clock Generator

IDT
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