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9ZX21201 데이터시트 PDF




IDT에서 제조한 전자 부품 9ZX21201은 전자 산업 및 응용 분야에서
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부품번호 9ZX21201 기능
기능 12-OUTPUT DIFFERENTIAL Z-BUFFER
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9ZX21201 데이터시트, 핀배열, 회로
DATASHEET
12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN2/3 AND QPI 9ZX21201
General Description
The IDT9ZX21201 is a 12-output DB1200Z suitable for PCI-Express
Gen3 or QPI applications. The part is backwards compatible to
PCIe Gen1 and Gen2. A fixed external feedback maintains low drift
for critical QPI applications. In bypass mode, the IDT9ZX21201 can
provide outputs up to 150MHz.
Recommended Application
12-output PCIe Gen3/ QPI differential buffer for Romley and newer
platforms
Key Specifications
• Cycle-to-cycle jitter <50ps
• Output-to-output skew < 65 ps
• Input-to-output delay variation <50ps
• PCIe Gen3 phase jitter < 1.0ps RMS
• QPI 9.6GT/s 12UI phase jitter < 0.2ps RMS
Features/Benefits
• Space-saving 64-pin packages
• Fixed feedback path/ 0ps input-to-output delay
• 9 Selectable SMBus Addresses/Mulitple devices can share
the same SMBus Segment
• 12 OE# pins/Hardware control of each output
• PLL or bypass mode/PLL can dejitter incoming clock
• 100MHz or 133MHz PLL mode operation/supports PCIe
and QPI applications
• Selectable PLL bandwidth/minimizes jitter peaking in
downstream PLL's
• Spread Spectrum Compatible/tracks spreading input clock
for low EMI
• Software control of PLL Bandwidth and Bypass Settings/
PLL can dejitter incoming clock (B Rev only)
Output Features
• 12 - 0.7V differential HCSL output pairs
Functional Block Diagram
OE(11:0)#
DIF_IN
DIF_IN#
HIBW_BYPM_LOBW#
100M_133M#
CKPWRGD/PD#
SMB_A0_tri
SMB_A1_tri
SMBDAT
SMBCLK
Logic
Z-PLL
(SS Compatible)
DFB_OUT
DIF(11:0)
Note: Even though the feedback is fixed, DFB_OUT still needs a
termination network for the part to function.
IDT® 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI
1
IREF
1682D - 11/19/15




9ZX21201 pdf, 반도체, 판매, 대치품
9ZX21201
12-Output Differential Z-buffer for PCIe Gen2/3 and QPI
Pin Description (continued)
33 GND
34 DIF_4
35 DIF_4#
36 vOE4#
37 vOE5#
38 DIF_5
39 DIF_5#
40 VDD
41 GND
42 DIF_6
43 DIF_6#
44 vOE6#
45 vOE7#
46 DIF_7
47 DIF_7#
48 GND
49 VDD
50 DIF_8
51 DIF_8#
52 vOE8#
53 vOE9#
54 DIF_9
55 DIF_9#
56 VDD
57 VDD
58 GND
59 DIF_10
60 DIF_10#
61 vOE10#
62 vOE11#
63 DIF_11
64 DIF_11#
PWR
OUT
OUT
IN
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
IN
OUT
OUT
PWR
PWR
PWR
OUT
OUT
IN
IN
OUT
OUT
Ground pin.
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 4
1 =disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 5. This pin has an internal pull-down
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
Ground pin.
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 6. This pin has an internal pull-down
1 =disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 7. This pin has an internal pull-down
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 8. This pin has an internal pull-down
1 =disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 9. This pin has an internal pull-down
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
Power supply, nominal 3.3V
Ground pin.
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 10. This pin has an internal pull-down
1 =disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 11. This pin has an internal pull-down
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
IDT® 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI
4
1682D- 11/19/15

4페이지










9ZX21201 전자부품, 판매, 대치품
9ZX21201
12-Output Differential Z-buffer for PCIe Gen2/3 and QPI
Electrical Characteristics - Skew and Differential Jitter Parameters
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
CLK_IN, DIF[x:0]
tSPO_PLL
Input-to-Output Skew in PLL mode
nominal value @ 25°C, 3.3V
-100 29
100 ps 1,2,4,5,8
CLK_IN, DIF[x:0]
tPD_BYP
Input-to-Output Skew in Bypass mode
nominal value @ 25°C, 3.3V
2.5 3.7 4.5 ns 1,2,3,5,8
CLK_IN, DIF[x:0]
tDSPO_PLL
Input-to-Output Skew Varation in PLL mode
across voltage and temperature
-50
50 ps 1,2,3,5,8
CLK_IN, DIF[x:0]
Input-to-Output Skew Varation in Bypass mode
tDSPO_BYP
across voltage and temperature
-250
250 ps 1,2,3,5,8
CLK_IN, DIF[x:0]
tDTE
Random Differential Tracking error beween two
9ZX devices in Hi BW Mode
2.9 5 ps 1,2,3,5,8
(rms)
CLK_IN, DIF[x:0]
Random Differential Spread Spectrum Tracking
tDSSTE error beween two 9ZX devices in Hi BW Mode
14 75 ps 1,2,3,5,8
DIF{x:0]
tSKEW_ALL
Output-to-Output Skew across all outputs
(Common to Bypass and PLL mode)
32 65 ps 1,2,3,8
PLL Jitter Peaking
PLL Jitter Peaking
PLL Bandwidth
PLL Bandwidth
Duty Cycle
Duty Cycle Distortion
jpeak-hibw
jpeak-lobw
pllHIBW
pllLOBW
tDC
tDCD
LOBW#_BYPASS_HIBW = 1
LOBW#_BYPASS_HIBW = 0
LOBW#_BYPASS_HIBW = 1
LOBW#_BYPASS_HIBW = 0
Measured differentially, PLL Mode
Measured differentially, Bypass Mode
@100MHz
0 1.8
0 0.7
2 3.1
0.7 1.1
45 49.6
-2 -0.2
2.5 dB 7,8
2 dB 7,8
4
MHz
8,9
1.4 MHz 8,9
55 % 1
2 % 1,10
Jitter, Cycle to cycle
tjcyc-cyc
PLL mode
Additive Jitter in Bypass Mode
15.7
0.1
50
50
ps 1,11
ps 1,11
Notes for preceding table:
1 Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.
2 Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.
3 All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.
4 This parameter is deterministic for a given device
5 Measured with scope averaging on to find mean value.
6.t is the period of the input clock
7 Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.
8. Guaranteed by design and characterization, not 100% tested in production.
9 Measured at 3 db down or half power point.
10 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
11 Measured from differential waveform
IDT® 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI
7
1682D- 11/19/15

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