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9ZXL0651 데이터시트 PDF




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부품번호 9ZXL0651 기능
기능 6-OUTPUT LOW-POWER HCSL BUFFER
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9ZXL0651 데이터시트, 핀배열, 회로
6-OUTPUT LOW-POWER HCSL BUFFER FOR PCIE GEN1-2-3 AND QPI
DATASHEET
9ZXL0651
General Description
The 9ZXL0651 is a low-power 6-output differential buffer
that meets all the performance requirements of the Intel
DB1200Z specification. It consumes 50% less power than
standard HCSL devices and has internal terminations to
allow direct connection to 85 ohm transmission lines. The
9ZXL0651 is backwards compatible to PCIe Gen1 and
Gen2 and QPI 6.4GT/s specifications. A fixed, internal
feedback path maintains low drift for critical QPI
applications.
Recommended Application
6-Output Low-Power HCSL Buffer for PCIe Gen1-2-3 and
QPI
Output Features
6 - 0.7V low-power HCSL (LP-HCSL) output pairs
w/integrated terminations
Block Diagram
Features/Benefits
Low-Power-HCSL outputs w/Zo = 85; save power and
board space - no termination resistors required. Ideal for
blade servers.
Space-saving 40-pin VFQFPN package
Fixed feedback path for 0ps input-to-output delay
6 OE# pins; Hardware control of each output
PLL or bypass mode; PLL can dejitter incoming clock
Selectable PLL bandwidth; minimizes jitter peaking in
downstream PLL's
Spread Spectrum Compatible; tracks spreading input
clock for low EMI
Key Specifications
Cycle-to-cycle jitter <50ps
Output-to-output skew <65 ps
Input-to-output delay variation <50ps
PCIe Gen3 phase jitter <1.0ps RMS
QPI 9.6GT/s 12UI phase jitter <0.2ps RMS
OE(5:0)#
DIF_IN
DIF_IN#
HIBW_BYPM_LOBW#
CKPWRGD/PD#
SMBDAT
SMBCLK
Logic
Z-PLL
(SS Compatible)
DFB_OUT_NC
DIF(5:0)
IDT® 6-OUTPUT LOW-POWER HCSL BUFFER FOR PCIE GEN1-2-3 AND QPI
1
9ZXL0651
REV C 040115




9ZXL0651 pdf, 반도체, 판매, 대치품
9ZXL0651
6-OUTPUT LOW-POWER HCSL BUFFER FOR PCIE GEN1-2-3 AND QPI
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9ZXL0651. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
PARAMETER
SYMBOL
CONDITIONS
VDD, VDDA,
3.3V Core Supply Voltage
VDDR
VDD for core logic and PLL
Input Low Voltage
VIL
Input High Voltage
VIH
Except for SMBus interface
Input High Voltage
VIHSMB
SMBus clock and data pins
Storage Temperature
Ts
Junction Temperature
Tj
Input ESD protection
ESD prot
Human Body Model
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
UNITS NOTES
MIN TYP MAX
GND-0.5
-65
2000
4.6
VDD+0.5V
5.5V
150
125
V
V
V
V
°C
°C
V
1,2
1
1
1
1
1
1
Electrical Characteristics–Clock Input Parameters
TA = TCOM; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
Input High Voltage - DIF_IN VIHDIF
Differential inputs
(single-ended measurement)
Input Low Voltage - DIF_IN
VILDIF
Differential inputs
(single-ended measurement)
Input Common Mode
Voltage - DIF_IN
VCOM
Common Mode Input Voltage
Input Amplitude - DIF_IN
VSWING
Peak to Peak value
(single-ended measurement)
Input Slew Rate - DIF_IN
dv/dt
Measured differentially
Input Leakage Current
IIN
VIN = VDD , VIN = GND
Input Duty Cycle
dtin Measurement from differential wavefrom
Input Jitter - Cycle to Cycle
JDIFIn
Differential Measurement
1 Guaranteed by design and characterization, not 100% tested in production.
2Slew rate measured through +/-75mV window centered around differential zero
MIN TYP
600 800
VSS - 300
300
0
300
0.35
-5
45 50
0
MAX UNITS NOTES
1150
mV
1
300 mV 1
1000
mV
1
1450
5
55
125
mV
V/ns
uA
%
ps
1
1,2
1
1
1
IDT® 6-OUTPUT LOW-POWER HCSL BUFFER FOR PCIE GEN1-2-3 AND QPI
4
9ZXL0651
REV C 040115

4페이지










9ZXL0651 전자부품, 판매, 대치품
9ZXL0651
6-OUTPUT LOW-POWER HCSL BUFFER FOR PCIE GEN1-2-3 AND QPI
Electrical Characteristics–Skew and Differential Jitter Parameters
TA = TCOM; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
CLK_IN, DIF[x:0]
tSPO_PLL
In-to-Out Skew in PLL mode @ 100MHz
nominal value @35°C, 3.3V
CLK_IN, DIF[x:0]
tPD_BYP
In-to-Out Skew in Bypass mode @ 100MHz
nominal value @ 35°C, 3.3V
CLK_IN, DIF[x:0]
tDSPO_PLL
In-to-Out Skew Varation in PLL mode
across voltage and temperature
CLK_IN, DIF[x:0]
tDSPO_BYP
In-to-Out Skew Varation in Bypass mode
across voltage and temperature
CLK_IN, DIF[x:0]
tDTE
Random Differential Tracking error beween two
9ZX devices in Hi BW Mode
MIN
-100
2.5
-50
-250
TYP
53
3.4
0
0
3
MAX
100
4.5
50
250
5
UNITS
ps
NOTES
1,2,4,5,8
ns 1,2,3,5,8
ps 1,2,3,5,8
ps
ps
(rms)
1,2,3,5,8
1,2,3,5,8
CLK_IN, DIF[x:0]
tDSSTE
Random Differential Spread Spectrum Tracking
error beween two 9ZX devices in Hi BW Mode
15 75
ps 1,2,3,5,8
DIF{x:0]
tSKEW_ALL
Output-to-Output Skew across all outputs
(Common to Bypass and PLL mode)
39 65
ps 1,2,3,8
PLL Jitter Peaking
jpeak-hibw
LOBW#_BYPASS_HIBW = 1
2.5 dB 7,8
PLL Jitter Peaking
PLL Bandwidth
jpeak-lobw
pllHIBW
LOBW#_BYPASS_HIBW = 0
LOBW#_BYPASS_HIBW = 1
2 dB 7,8
4
MHz
8,9
PLL Bandwidth
pllLOBW
LOBW#_BYPASS_HIBW = 0
1.4 MHz
8,9
Duty Cycle
Duty Cycle Distortion
tDC
tDCD
Measured differentially, PLL Mode
Measured differentially, Bypass Mode
@100MHz
45 50.1 55
-1.7 |2|
%1
% 1,10
Jitter, Cycle to cycle
tjcyc-cyc
PLL mode
Additive Jitter in Bypass Mode
14 50
0 25
ps 1,11
ps 1,11
Notes for preceding table:
1 CL = 2pF, Zo = 85differential trace impedance. Input to output skew is measured at the first output edge following the corresponding input.
2 Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.
3 All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.
4 This parameter is deterministic for a given device
5 Measured with scope averaging on to find mean value.
6.t is the period of the input clock
7 Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.
8. Guaranteed by design and characterization, not 100% tested in production.
9 Measured at 3 db down or half power point.
10 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
11 Measured from differential waveform
IDT® 6-OUTPUT LOW-POWER HCSL BUFFER FOR PCIE GEN1-2-3 AND QPI
7
9ZXL0651
REV C 040115

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9ZXL0651

6-OUTPUT LOW-POWER HCSL BUFFER

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