PDF 9ZXL1230 Data sheet ( Hoja de datos )

Número de pieza	9ZXL1230
Descripción	12-OUTPUT LOW POWER DIFFERENTIAL BUFFER
Fabricantes	IDT
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No Preview Available ! DATASHEET 12-OUTPUT LOW POWER DIFFERENTIAL BUFFER FOR PCIE GEN3 AND QPI 9ZXL1230 General Description The 9ZXL1230 is a small-footprint, low power 12-output differential buffer that meets all the performance requirements of the Intel DB1900Z specification. It is pin compatible to the 9ZX21200. The 9ZXL1230 is backwards compatible to PCIe Gen2 and QPI 6.4GT/s specifications. A fixed, internal feedback path maintains low drift for critical QPI applications. Recommended Application 12-output Low Power PCIe Gen3/QPI differential buffer for Romley Output Features • 12 - 0.7V low-power HCSL-compatible output pairs Block Diagram Features/Benefits • Low-power push-pull outputs; Save power and board space - no Rp • Pin compatible to 9ZX21200; easy path to >50% power savings • Space-saving 56-pin QFN package • Fixed feedback path for 0ps input-to-output delay • 9 Selectable SMBus Addresses; Mulitple devices can share the same SMBus Segment • 4 OE# pins; Hardware control of four outputs, other outputs free run • PLL or bypass mode; PLL can dejitter incoming clock • 100MHz or 133MHz PLL mode operation; supports PCIe and QPI applications • Selectable PLL bandwidth; minimizes jitter peaking in downstream PLL's • Spread Spectrum Compatible; tracks spreading input clock for low EMI Key Specifications • Cycle-to-cycle jitter <50ps • Output-to-output skew <65 ps • Input-to-output delay variation <50ps • PCIe Gen3 phase jitter <1.0ps RMS • QPI 9.6GT/s 12UI phase jitter <0.2ps RMS OE(8,6,4,2)# DIF_IN DIF_IN# Z-PLL (SS Compatible) DFB_OUT_NC DIF(11:0) HIBW_BYPM_LOBW# 100M_133M# CKPWRGD/PD# SMB_A0_tri SMB_A1_tri SMBDAT SMBCLK Logic IDT® 12-OUTPUT LOW POWER DIFFERENTIAL BUFFER FOR PCIE GEN3 AND QPI 1 9ZXL1230 REV B 041112 1 page 9ZXL1230 12-OUTPUT LOW POWER DIFFERENTIAL BUFFER FOR PCIE GEN3 AND QPI Pin Descriptions (cont.) 32 OE4# 33 DIF_5 34 DIF_5# 35 VDD 36 GND 37 DIF_6 38 DIF_6# 39 OE6# 40 DIF_7 41 DIF_7# 42 GND 43 VDDIO 44 DIF_8 45 DIF_8# 46 OE8# 47 DIF_9 48 DIF_9# 49 VDDIO 50 VDD 51 GND 52 DIF_10 53 DIF_10# 54 DIF_11 55 DIF_11# 56 VDDA IN OUT OUT PWR PWR OUT OUT IN OUT OUT PWR PWR OUT OUT IN OUT OUT PWR PWR PWR OUT OUT OUT OUT PWR Active low input for enabling DIF pair 4 1 =disable outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential Complementary clock output Power supply, nominal 3.3V Ground pin. 0.7V differential true clock output 0.7V differential Complementary clock output Active low input for enabling DIF pair 6. 1 =disable outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential Complementary clock output Ground pin. Power supply for differential outputs 0.7V differential true clock output 0.7V differential Complementary clock output Active low input for enabling DIF pair 8. 1 =disable outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential Complementary clock output Power supply for differential outputs Power supply, nominal 3.3V Ground pin. 0.7V differential true clock output 0.7V differential Complementary clock output 0.7V differential true clock output 0.7V differential Complementary clock output 3.3V power for the PLL core. IDT® 12-OUTPUT LOW POWER DIFFERENTIAL BUFFER FOR PCIE GEN3 AND QPI 5 9ZXL1230 REV B 041112 5 Page 9ZXL1230 12-OUTPUT LOW POWER DIFFERENTIAL BUFFER FOR PCIE GEN3 AND QPI Clock Periods–Differential Outputs with Spread Spectrum Disabled SSC OFF Center Freq. MH z 1 Clock -c2c jitter DIF 1 00.0 0 1 33.3 3 9.94 900 7.44 925 1us -SSC Sh 0.1s - ppm L 9. 9990 0 7. 4992 5 Measurement Window 0 .1s 0.1s 0 ppm Period Nominal + ppm L 10.0 0000 10 .001 00 7.5 0000 7 .5007 5 1us +SSC Sh 1 Clock +c2c jitter 10.0 5100 7.55 075 Units Notes ns 1,2,3 ns 1,2,4 Clock Periods–Differential Outputs with Spread Spectrum Enabled Measurement Window SSC ON DIF Center Freq. MH z 99.75 1 33.0 0 1 Clock -c2c jitter Abs Per M in 9.94 906 7.44 930 1us -SSC Short-Term Average M in 9.999 06 7.499 30 0.1s - ppm Long-Term Av erage Min 10 .0240 6 7. 5180 5 0 .1s 0 ppm Period Nominal 10.0 2506 7.5 1880 0.1s + ppm Long-Te rm Av era ge Max 10 .026 07 7 .5195 5 1us +SSC Short-Term Average Ma x 1 0.05 107 7.538 30 1 Clock +c2c jitter A bs Per Ma x Units Notes 10.1 0107 7.58 830 ns 1,2,3 ns 1,2,4 Notes: 1Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ/CK410B+ accuracy requirements (+/-100ppm). The 9ZXL1230 itself does not contribute to ppm error. 3 Driven by SRC output of main clock, 100 MHz PLL Mode or Bypass mode 4 Driven by CPU output of main clock, 133 MHz PLL Mode or Bypass mode Differential Output Terminations DIF Zo (Ω) Rs (Ω) 100 33 85 27 9ZXL Differential Test Loads Low-Power HCSL- Compatible Output buffer Rs Rs 10 inches 85ohm Differential Zo 2pF 2pF IDT® 12-OUTPUT LOW POWER DIFFERENTIAL BUFFER FOR PCIE GEN3 AND QPI 11 9ZXL1230 REV B 041112 11 Page

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