Datasheet.kr   

9ZX21901B 데이터시트 PDF




IDT에서 제조한 전자 부품 9ZX21901B은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 9ZX21901B 자료 제공

부품번호 9ZX21901B 기능
기능 19-Output Differential Zbuffer
제조업체 IDT
로고 IDT 로고


9ZX21901B 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 18 페이지수

미리보기를 사용할 수 없습니다

9ZX21901B 데이터시트, 핀배열, 회로
DATASHEET
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI
9ZX21901B
Description
Features/Benefits
The 9ZX21901 is a version of the Intel DB1900Z Differential Buffer
with an ajdustable external feedback path allowing the user to
eliminate trace delays from their design. It is suitable for PCIe Gen3
or QPI applications. The part is backwards compatible to PCIe
Gen1 and Gen2. The device maintains low drift for critical QPI
applications. In bypass mode, the IDT9ZX21901 can provide outputs
up to 400MHz.
Recommended Application
19 output PCIe Gen3/QPI buffer with adjustable feedback for Romley
platforms
Output Features
• 19 - 0.7V current mode differential HCSL output pairs
External feedback path; Adjustable input-to-output delay
9 Selectable SMBus addresses/ Multiple devices can
share same SMBus segment
8 dedicated OE# pins/ hardware control of outputs
PLL or bypass mode/ PLL can dejitter incoming clock
Selectable PLL BW/ minimizes jitter peaking in
downstream PLL's
Spread spectrum compatible/tracks spreading input clock
for EMI reduction
SMBus Interface/ unused outputs can be disabled
100MHz & 133.33MHz PLL mode/ Legacy QPI support
Undriven differential outputs in Power Down mode for
maximum power savings
Key Specifications
• Cycle-to-cycle jitter: < 50ps
• Output-to-output skew: <65ps
• Input-to-output delay: User adjustable
• Input-to-output delay variation: <50ps
• Phase jitter: PCIe Gen3 < 1ps rms
Functional Block Diagram
• Phase jitter: QPI 9.6GB/s < 0.2ps rms
OE(5_12)#
8
DIF_IN
DIF_IN#
DFB_IN
DFB_IN#
HIBW_BYPM_LOBW#
100M_133M#
CKPWRGD/PD#
SMB_A0_tri
SMB_A1_tri
SMBDAT
SMBCLK
Logic
Z-PLL
(SS Compatible)
DFB_OUT
DIF(18:0)
IREF
IDT® 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI
1
1586P - 11/19/15




9ZX21901B pdf, 반도체, 판매, 대치품
9ZX21901B
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI
Pin Description (continued)
PIN #
PIN NAME
PIN TYPE
37 OE6#
IN
38 DIF_7
39 DIF_7#
OUT
OUT
40 OE7#
IN
41 DIF_8
42 DIF_8#
OUT
OUT
43 OE8#
IN
44 GND
45 VDD
46 DIF_9
47 DIF_9#
PWR
PWR
OUT
OUT
48 OE9#
IN
49 DIF_10
50 DIF_10#
OUT
OUT
51 OE10#
IN
52 DIF_11
53 DIF_11#
OUT
OUT
54 OE11#
IN
55 DIF_12
56 DIF_12#
OUT
OUT
57 OE12#
IN
58 VDD
59 DIF_13
60 DIF_13#
61 DIF_14
62 DIF_14#
63 GND
64 DIF_15
65 DIF_15#
66 DIF_16
67 DIF_16#
68 VDD
69 DIF_17
70 DIF_17#
71 DIF_18
72 DIF_18#
PWR
OUT
OUT
OUT
OUT
PWR
OUT
OUT
OUT
OUT
PWR
OUT
OUT
OUT
OUT
DESCRIPTION
Active low input for enabling DIF pair 6.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 7.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 8.
1 =disable outputs, 0 = enable outputs
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 9.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 10.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 11.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 12.
1 =disable outputs, 0 = enable outputs
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential Complementary clock output
0.7V differential true clock output
0.7V differential Complementary clock output
Ground pin.
0.7V differential true clock output
0.7V differential Complementary clock output
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential Complementary clock output
0.7V differential true clock output
0.7V differential Complementary clock output
IDT® 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI
4
1586P - 11/19/15

4페이지










9ZX21901B 전자부품, 판매, 대치품
9ZX21901B
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI
Electrical Characteristics - Current Consumption
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
Operating Supply Current
Powerdown Current
IDD3.3OP
IDD3.3PDZ
All outputs active @100MHz, CL = Full load;
All differential pairs tri-stated
1Guaranteed by design and characterization, not 100% tested in production.
407 500 mA 1
12 36 mA 1
Electrical Characteristics - Skew and Differential Jitter Parameters
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
CLK_IN, DIF[x:0]
tSPO_PLL
Input-to-Output Skew in PLL mode
nominal value @ 25°C, 3.3V
-300 -200
-100
ps 1,2,4,5,8
CLK_IN, DIF[x:0]
tPD_BYP
Input-to-Output Skew in Bypass mode
nominal value @ 25°C, 3.3V
2.5 3.5 4.5 ns 1,2,3,5,8
CLK_IN, DIF[x:0]
tDSPO_PLL
Input-to-Output Skew Varation in PLL mode
across voltage and temperature
-50
0
50 ps 1,2,3,5,8
CLK_IN, DIF[x:0]
Input-to-Output Skew Varation in Bypass mode
tDSPO_BYP
across voltage and temperature
-250
250 ps 1,2,3,5,8
CLK_IN, DIF[x:0]
tDTE
Random Differential Tracking error beween two
9ZX devices in Hi BW Mode
3 5 ps 1,2,3,5,8
(rms)
CLK_IN, DIF[x:0]
Random Differential Spread Spectrum Tracking
tDSSTE error beween two 9ZX devices in Hi BW Mode
15 75 ps 1,2,3,5,8
DIF{x:0]
tSKEW_ALL
Output-to-Output Skew across all outputs
(Common to Bypass and PLL mode)
45 65 ps 1,2,3,8
PLL Jitter Peaking
PLL Jitter Peaking
PLL Bandwidth
PLL Bandwidth
Duty Cycle
Duty Cycle Distortion
Jitter, Cycle to cycle
jpeak-hibw
jpeak-lobw
pllHIBW
pllLOBW
tDC
tDCD
tjcyc-cyc
LOBW#_BYPASS_HIBW = 1
LOBW#_BYPASS_HIBW = 0
LOBW#_BYPASS_HIBW = 1
LOBW#_BYPASS_HIBW = 0
Measured differentially, PLL Mode
Measured differentially, Bypass Mode
@100MHz
PLL mode
Additive Jitter in Bypass Mode
0 1 2.5 dB 7,8
01
2 dB 7,8
23
4
MHz
8,9
0.7 1
1.4 MHz 8,9
45 50 55 % 1
-2 0
2 % 1,10
24 50 ps 1,11
20 50 ps 1,11
Notes for preceding table:
1 Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input. Feedback
path is 695 mils long.
2 Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.
3 All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.
4 This parameter is deterministic for a given device
5 Measured with scope averaging on to find mean value. DIF_IN slew rate must be matched to DIF output slew rate.
6.t is the period of the input clock
7 Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.
8. Guaranteed by design and characterization, not 100% tested in production.
9 Measured at 3 db down or half power point.
10 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
11 Measured from differential waveform
IDT® 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI
7
1586P - 11/19/15

7페이지


구       성 총 18 페이지수
다운로드[ 9ZX21901B.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
9ZX21901B

19-Output Differential Zbuffer

IDT
IDT
9ZX21901C

19-Output Differential Zbuffer

IDT
IDT

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵