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부품번호 | 9ZXL1231 기능 |
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기능 | 12-output DB1200ZL | ||
제조업체 | IDT | ||
로고 | |||
전체 18 페이지수
12-output DB1200ZL
9ZXL1231
DATASHEET
General Description
The 9ZXL1231 meets the demanding requirements of the
Intel DB1200ZL specification, including the critical low-drift
requirements of Intel CPUs.
Recommended Application
Buffer for Romley, Grantley and Purley Servers, solid state
storage and PCIe
Output Features
• 12 - Low-Power (LP) HCSL output pairs
Key Specifications
• Cycle-to-cycle jitter <50ps
• Output-to-output skew <50 ps
• Input-to-output delay variation <50ps
• PCIe Gen3 phase jitter <1.0ps RMS
• Phase jitter: QPI/UPI >=9.6GB/s <0.2ps rms
Block Diagram
OE(11:0)#
Features/Benefits
• Low-power push-pull HCSL outputs; eliminate 24 resistors,
save 41mm2 of area
• Pin compatible to 9ZX21201; easy path to >50% power
savings
• Space-saving 64 VFQFPN package
• Fixed feedback path for 0ps input-to-output delay
• 9 Selectable SMBus Addresses; multiple devices can
share the same SMBus Segment
• 12 OE# pins; hardware control of each output
• PLL or bypass mode; PLL can dejitter incoming clock
• Selectable PLL bandwidth; minimizes jitter peaking in
downstream PLL's
• Spread Spectrum Compatible; tracks spreading input clock
for low EMI
DIF_IN
DIF_IN#
Z-PLL
(SS Compatible)
DFB_OUT_NC
DIF(11:0)
HIBW_BYPM_LOBW#
100M_133M#
CKPWRGD/PD#
SMB_A0_tri
SMB_A1_tri
SMBDAT
SMBCLK
Logic
9ZXL1231 REVISION J 05/25/16
1 ©2016 Integrated Device Technology, Inc.
9ZXL1231 DATASHEET
Pin Descriptions
PIN #
PIN NAME
1 VDDA
2 GNDA
3 NC
4 100M_133M#
5 HIBW_BYPM_LOBW#
6 CKPWRGD_PD#
7 GND
8 VDDR
9 DIF_IN
10 DIF_IN#
11 SMB_A0_tri
12 SMBDAT
13 SMBCLK
14 SMB_A1_tri
15 DFB_OUT_NC#
16 DFB_OUT_NC
17 DIF_0
18 DIF_0#
19 vOE0#
20 vOE1#
21 DIF_1
22 DIF_1#
23 GND
24 VDD
25 VDDIO
26 DIF_2
27 DIF_2#
28 vOE2#
29 vOE3#
30 DIF_3
31 DIF_3#
32 VDDIO
33 GND
34 DIF_4
35 DIF_4#
36 vOE4#
37 vOE5#
TYPE
PWR
GND
N/A
IN
IN
IN
GND
PWR
IN
IN
IN
I/O
IN
IN
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
GND
PWR
PWR
OUT
OUT
IN
IN
OUT
OUT
PWR
GND
OUT
OUT
IN
IN
DESCRIPTION
Power for the PLL core.
Ground pin for the PLL core.
No Connection.
3.3V Input to select operating frequency.
See Functionality Table for Definition
Trilevel input to select High BW, Bypass or Low BW mode.
See PLL Operating Mode Table for Details.
3.3V Input notifies device to sample latched inputs and start up on first high assertion, or exit Power Down
Mode on subsequent assertions. Low enters Power Down Mode.
Ground pin.
3.3V power for differential input clock (receiver). This VDD should be treated as an analog power rail and
filtered appropriately.
HCSL True input
HCSL Complementary Input
SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A1 to decode 1 of 9
SMBus Addresses.
Data pin of SMBUS circuitry, 5V tolerant
Clock pin of SMBUS circuitry, 5V tolerant
SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A0 to decode 1 of 9
SMBus Addresses.
Complementary half of differential feedback output, provides feedback signal to the PLL for
synchronization with input clock to eliminate phase error. This pin should NOT be connected on the circuit
board, the feedback is internal to the package.
True half of differential feedback output, provides feedback signal to the PLL for synchronization with the
input clock to eliminate phase error. This pin should NOT be connected on the circuit board, the feedback
is internal to the package.
HCSL true clock output
HCSL Complementary clock output
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
HCSL true clock output
HCSL Complementary clock output
Ground pin.
Power supply, nominal 3.3V
Power supply for differential outputs
HCSL true clock output
HCSL Complementary clock output
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
HCSL true clock output
HCSL Complementary clock output
Power supply for differential outputs
Ground pin.
HCSL true clock output
HCSL Complementary clock output
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
12-OUTPUT DB1200ZL
4
REVISION J 05/25/16
4페이지 9ZXL1231 DATASHEET
Electrical Characteristics–Input/Supply/Common Output Parameters
TAMB = TCOM or TIND, unless noted., Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
Supply Voltage
Output Supply Voltage
Ambient Operating
Temperature
Input High Voltage
Input Low Voltage
Input High Voltage
Input Mid Voltage
Input Low Voltage
VDDx
VDDIO
TAMB
VIH
VIL
VIHTRI
VIMTRI
VILTRI
IIN
Supply voltage, except VDDIO
Supply voltage for DIF outputs, if present
Commmercial range (TCOM)
Industrial range (TIND)
Single-ended inputs, except SMBus, tri-level
inputs
Single-ended inputs, except SMBus, tri-level
inputs
Tri-Level Inputs
Tri-Level Inputs
Tri-Level Inputs
Single-ended inputs, VIN = GND, VIN = VDD
3.135
0.95
0
-40
2
3.3
1.05
3.465
3.465
70
85
VDD + 0.3
GND - 0.3
0.8
2.2
1.2
GND - 0.3
-5
VDD/2
VDD + 0.3
1.8
0.8
5
V
V
°C
°C
V
V
V
V
V
uA
Input Current
Single-ended inputs
IINP
VIN = 0 V; Inputs with internal pull-up resistors
-200
VIN = VDD; Inputs with internal pull-down resistors
200 uA
Input Frequency
Pin Inductance
Capacitance
Fibyp
Fipll
Fipll
Lpin
CIN
CINDIF_IN
VDD = 3.3 V, Bypass mode
VDD = 3.3 V, 100MHz PLL mode
VDD = 3.3 V, 133.33MHz PLL mode
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
COUT
Output pin capacitance
Clk Stabilization
Input SS Modulation
Frequency PCIe
OE# Latency
TSTAB
fMODINPCIe
tLATOE#
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Allowable Frequency for PCIe Applications
(Triangular Modulation)
DIF start after OE# assertion
DIF stop after OE# deassertion
Tdrive_PD#
tDRVPD
DIF output enable after
PD# de-assertion
Tfall
tF
Fall time of control inputs
Trise
tR
Rise time of control inputs
1Guaranteed by design and characterization, not 100% tested in production.
2Control input must be monotonic from 20% to 80% of input swing.
3Time from deassertion until outputs are >200 mV
4DIF_IN input
33 150
90 100.00 110
120 133.33 147
7
1.5 5
1.5 2.7
6
0.18
1.8
MHz
MHz
MHz
nH
pF
pF
pF
ms
1
1
1,4
1
1,2
30 33 kHz
4 10 clocks 1,2,3
300 us 1,3
5 ns 2
5 ns 2
REVISION J 05/25/16
7
12-OUTPUT DB1200ZL
7페이지 | |||
구 성 | 총 18 페이지수 | ||
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부품번호 | 상세설명 및 기능 | 제조사 |
9ZXL1230 | 12-OUTPUT LOW POWER DIFFERENTIAL BUFFER | IDT |
9ZXL1231 | 12-output DB1200ZL | IDT |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |