Datasheet.kr   

9ZXL1251 데이터시트 PDF




IDT에서 제조한 전자 부품 9ZXL1251은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 9ZXL1251 자료 제공

부품번호 9ZXL1251 기능
기능 12-output DB1200ZL Derivative
제조업체 IDT
로고 IDT 로고


9ZXL1251 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 20 페이지수

미리보기를 사용할 수 없습니다

9ZXL1251 데이터시트, 핀배열, 회로
12-output DB1200ZL Derivative with
Integrated 85Terminations
9ZXL1251
DATASHEET
General Description
The 9ZXL1251 meets the demanding requirements of the
Intel DB1200ZL specification, including the critical low-drift
requirements of Intel CPUs. It is pin compatible to the
9ZXL1231 and integrates 24 termination resistors, saving
41mm2 board area.
Recommended Application
Buffer for Romley, Grantley and Purley Servers, solid state
storage and PCIe
Output Features
12 LP-HCSL Output Pairs w/integrated terminations (Zo =
85)
Key Specifications
Cycle-to-cycle jitter <50ps
Output-to-output skew <50ps
Input-to-output delay variation <50ps
PCIe Gen3 phase jitter <1.0ps RMS
Phase jitter: QPI/UPI >=9.6GB/s <0.2ps rms
Features/Benefits
85Low-power push-pull HCSL outputs; eliminate 24
resistors, save 41mm2 of area
Pin compatible to 9ZX21201 and 9ZXL1231; easy path to
power and area savings
Space-saving 64-pin VFQFPN package
Fixed feedback path for 0ps input-to-output delay
9 Selectable SMBus Addresses; multiple devices can
share the same SMBus Segment
12 OE# pins; hardware control of each output
PLL or bypass mode; supports common and separate clock
architectures
Selectable PLL bandwidth; minimizes jitter peaking in
downstream PLL's
Spread Spectrum Compatible; tracks spreading input clock
for low EMI
-40°C to +85°C device available; supports demanding
environmental applications
Block Diagram
OE(11:0)#
DIF_IN
DIF_IN#
Z-PLL
(SS Compatible)
DFB_OUT_NC
DIF(11:0)
HIBW_BYPM_LOBW#
100M_133M#
CKPWRGD/PD#
SMB_A0_tri
SMB_A1_tri
SMBDAT
SMBCLK
Logic
9ZXL1251 REVISION B 11/20/15 1 ©2015 Integrated Device Technology, Inc.




9ZXL1251 pdf, 반도체, 판매, 대치품
9ZXL1251 DATASHEET
Pin Descriptions
PIN #
PIN NAME
TYPE
DESCRIPTION
1 VDDA
PWR Power for the PLL core.
2 GNDA
GND Ground pin for the PLL core.
3 NC
N/A No Connection.
4 ^100M_133M#
IN 3.3V Input to select operating frequency. This pin has an internal pull-up resistor.
See Functionality Table for Definition
5 ^vHIBW_BYPM_LOBW# LATCHED Trilevel input to select High BW, Bypass or Low BW mode. This pin is biased to VDD/2
IN (Bypass mode) with internal pull up/pull down resistors. See PLL Operating Mode Table for
6 CKPWRGD_PD#
IN 3.3V Input notifies device to sample latched inputs and start up on first high assertion, or exit
Power Down Mode on subsequent assertions. Low enters Power Down Mode.
7 GND
GND Ground pin.
8 VDDR
PWR 3.3V power for differential input clock (receiver). This VDD should be treated as an analog power
rail and filtered appropriately.
9 DIF_IN
IN HCSL True input
10 DIF_IN#
IN HCSL Complementary Input
11 vSMB_A0_tri
IN SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A1 to
decode 1 of 9 SMBus Addresses. It has an internal 120Kohm pull down resistor.
12 SMBDAT
I/O Data pin of SMBUS circuitry, 5V tolerant
13 SMBCLK
IN Clock pin of SMBUS circuitry, 5V tolerant
14 vSMB_A1_tri
IN SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A0 to
decode 1 of 9 SMBus Addresses. It has an internal 120Kohm pull down resistor.
Complementary half of differential feedback output, provides feedback signal to the PLL for
15 DFB_OUT_NC#
OUT synchronization with input clock to eliminate phase error. This pin should NOT be connected on
the circuit board, the feedback is internal to the package.
True half of differential feedback output, provides feedback signal to the PLL for synchronization
16 DFB_OUT_NC
OUT with the input clock to eliminate phase error. This pin should NOT be connected on the circuit
board, the feedback is internal to the package.
17 DIF_0
OUT HCSL true clock output
18 DIF_0#
OUT HCSL Complementary clock output
19 vOE0#
IN
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
20 vOE1#
IN Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
21 DIF_1
OUT HCSL true clock output
22 DIF_1#
OUT HCSL Complementary clock output
23 GND
GND Ground pin.
24 VDD
PWR Power supply, nominal 3.3V
25 VDDIO
PWR Power supply for differential outputs
26 DIF_2
OUT HCSL true clock output
27 DIF_2#
OUT HCSL Complementary clock output
28 vOE2#
IN Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
29 vOE3#
IN
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
30 DIF_3
OUT HCSL true clock output
31 DIF_3#
OUT HCSL Complementary clock output
32 VDDIO
PWR Power supply for differential outputs
33 GND
GND Ground pin.
34 DIF_4
OUT HCSL true clock output
35 DIF_4#
OUT HCSL Complementary clock output
36 vOE4#
IN Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
37 vOE5#
Active low input for enabling DIF pair 5. This pin has an internal pull-down.
IN 1 =disable outputs, 0 = enable outputs
12-OUTPUT DB1200ZL DERIVATIVE WITH INTEGRATED 85TERMINATIONS 4
REVISION B 11/20/15

4페이지










9ZXL1251 전자부품, 판매, 대치품
9ZXL1251 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters
TAMB = TCOM or TIND, unless noted., Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
Supply Voltage
Output Supply Voltage
Ambient Operating
Temperature
Input High Voltage
Input Low Voltage
Input High Voltage
Input Mid Voltage
Input Low Voltage
VDDx
VDDIO
TAMB
VIH
VIL
VIHTRI
VIMTRI
VILTRI
IIN
Supply voltage, except VDDIO
Supply voltage for DIF outputs, if present
Commmercial range (TCOM)
Industrial range (TIND)
Single-ended inputs, except SMBus, tri-level
inputs
Single-ended inputs, except SMBus, tri-level
inputs
Tri-Level Inputs
Tri-Level Inputs
Tri-Level Inputs
Single-ended inputs, VIN = GND, VIN = VDD
3.135
0.95
0
-40
2
3.3
1.05
3.465
3.465
70
85
VDD + 0.3
GND - 0.3
0.8
2.2
1.2
GND - 0.3
-5
VDD/2
VDD + 0.3
1.8
0.8
5
V
V
°C
°C
V
V
V
V
V
uA
Input Current
Single-ended inputs
IINP
VIN = 0 V; Inputs with internal pull-up resistors
-200
VIN = VDD; Inputs with internal pull-down resistors
200 uA
Input Frequency
Pin Inductance
Capacitance
Fibyp
Fipll
Fipll
Lpin
CIN
CINDIF_IN
VDD = 3.3 V, Bypass mode
VDD = 3.3 V, 100MHz PLL mode
VDD = 3.3 V, 133.33MHz PLL mode
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
33 150
90 100.00 110
120 133.33 147
7
1.5 5
1.5 2.7
MHz
MHz
MHz
nH
pF
pF
1
1
1,4
COUT
Output pin capacitance
Clk Stabilization
TSTAB
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Input SS Modulation
Frequency PCIe
fMODINPCIe
Allowable Frequency for PCIe Applications
(Triangular Modulation)
OE# Latency
tLATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
Tdrive_PD#
tDRVPD
DIF output enable after
PD# de-assertion
Tfall
tF
Fall time of control inputs
Trise
tR
Rise time of control inputs
1Guaranteed by design and characterization, not 100% tested in production.
2Control input must be monotonic from 20% to 80% of input swing.
3Time from deassertion until outputs are >200 mV
4DIF_IN input
30
4
0.18
6 pF 1
1.8 ms 1,2
33 kHz
10 clocks 1,2,3
300 us 1,3
5 ns 2
5 ns 2
REVISION B 11/20/15
7 12-OUTPUT DB1200ZL DERIVATIVE WITH INTEGRATED 85TERMINATIONS

7페이지


구       성 총 20 페이지수
다운로드[ 9ZXL1251.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
9ZXL1251

12-output DB1200ZL Derivative

IDT
IDT

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵