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9ZXL1950 데이터시트 PDF




IDT에서 제조한 전자 부품 9ZXL1950은 전자 산업 및 응용 분야에서
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부품번호 9ZXL1950 기능
기능 19-output DB1900Z Low-Power Derivative
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9ZXL1950 데이터시트, 핀배열, 회로
19-output DB1900Z Low-Power Derivative
w/85ohm Terminations
9ZXL1950
DATASHEET
General Description
The 9ZXL1950 is a DB1900Z derivative buffer utilizing
Low-Power HCSL (LP-HCSL) outputs to increase edge rates
on long traces, reduce board space, and reduce power
consumption more than 50% from the original 9ZX21901.It is
pin-compatible to the 9ZXL1930 and fully integrates the
output terminations. It is suitable for PCI-Express Gen1/2/3 or
QPI/UPI applications, and uses a fixed external feedback to
maintain low drift for demanding QPI/UPI applications.
Recommended Application
Buffer for Romley, Grantley and Purley Servers
Output Features
19 LP-HCSL output pairs w/integrated terminations (Zo =
85
Key Specifications
Cycle-to-cycle jitter: <50ps
Output-to-output skew: <50ps
Input-to-output delay variation: <50ps
Phase jitter: PCIe Gen3 <1ps rms
Phase jitter: QPI/UPI 9.6GB/s <0.2ps rms
Features/Benefits
LP-HCSL outputs; up to 90% IO power reduction, better
signal integrity over long traces
Direct connect to 85transmission lines; eliminates 76
termination resistors, saves 130mm2 area
Pin compatible to the 9ZXL1930; easy upgrade to reduced
board space
72-pin VFQFPN package; smallest 19-output Z-buffer
Fixed feedback path; ~0ps input-to-output delay
9 Selectable SMBus addresses; multiple devices can share
same SMBus segment
Separate VDDIO for outputs; allows maximum power
savings
PLL or bypass mode; PLL can dejitter incoming clock
100MHz & 133.33MHz PLL mode; legacy QPI support
Selectable PLL BW; minimizes jitter peaking in downstream
PLL's
Spread spectrum compatible; tracks spreading input clock
for EMI reduction
SMBus Interface; unused outputs can be disabled
Block Diagram
DIF_IN
DIF_IN#
HIBW_BYPM_LOBW#
100M_133M#
CKPWRGD/PD#
SMB_A0_tri
SMB_A1_tri
SMBDAT
SMBCLK
Logic
Z-PLL
(SS Compatible)
FBOUT_NC
DIF(18:0)
9ZXL1950 REVISION E 11/20/15 1 ©2015 Integrated Device Technology, Inc.




9ZXL1950 pdf, 반도체, 판매, 대치품
9ZXL1950 DATASHEET
Pin Descriptions (cont.)
PIN #
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
PIN NAME
DIF7
DIF7#
GND
VDDIO
DIF8
DIF8#
DIF9
DIF9#
VDD
GND
DIF10
DIF10#
DIF11
DIF11#
GND
VDDIO
DIF12
DIF12#
DIF13
DIF13#
VDDIO
GND
DIF14
DIF14#
DIF15
DIF15#
GND
VDD
DIF16
DIF16#
DIF17
DIF17#
VDDIO
GND
DIF18
DIF18#
epad
PIN TYPE
OUT
OUT
GND
PWR
OUT
OUT
OUT
OUT
PWR
GND
OUT
OUT
OUT
OUT
GND
PWR
OUT
OUT
OUT
OUT
PWR
GND
OUT
OUT
OUT
OUT
GND
PWR
OUT
OUT
OUT
OUT
PWR
GND
OUT
OUT
GND
DESCRIPTION
Differential true clock output
Differential Complementary clock output
Ground pin.
Power supply for differential outputs
Differential true clock output
Differential Complementary clock output
Differential true clock output
Differential Complementary clock output
Power supply, nominal 3.3V
Ground pin.
Differential true clock output
Differential Complementary clock output
Differential true clock output
Differential Complementary clock output
Ground pin.
Power supply for differential outputs
Differential true clock output
Differential Complementary clock output
Differential true clock output
Differential Complementary clock output
Power supply for differential outputs
Ground pin.
Differential true clock output
Differential Complementary clock output
Differential true clock output
Differential Complementary clock output
Ground pin.
Power supply, nominal 3.3V
Differential true clock output
Differential Complementary clock output
Differential true clock output
Differential Complementary clock output
Power supply for differential outputs
Ground pin.
Differential true clock output
Differential Complementary clock output
Connect EPAD to ground.
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS 4
REVISION E 11/20/15

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9ZXL1950 전자부품, 판매, 대치품
9ZXL1950 DATASHEET
Electrical Characteristics–DIF 0.7V Low Power Differential Outputs
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
Slew rate
Slew rate matching
Trf
Trf
Scope averaging on
Slew rate matching.
1.5 2.7
8.8
4 V/ns 1, 2, 3
20 % 1, 2, 4
Voltage High
Voltage Low
VHigh
VLow
Statistical measurement on single-ended signal 660 787 850
using oscilloscope math function. (Scope
mV
averaging on)
-150 33 150
Max Voltage
Min Voltage
Crossing Voltage (abs)
Crossing Voltage (var)
Vmax
Vmin
Vcross_abs
-Vcross
Single ended signal using absolute value.
Includes 300mV of over/undershoot. (Scope
Scope averaging off
Scope averaging off
845 1150
mV
-300 9
250 471 550 mV
14 140 mV
1, 5
1, 6
1Guaranteed by design and characterization, not 100% tested in production. CL = 2pF with Zo = 85differential trace impedance.
2 Measured from differential waveform
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting -Vcross to be smaller than Vcross absolute.
Clock Periods–Differential Outputs with Spread Spectrum Disabled
SSC OFF
DIF
Center
Freq.
MHz
100.00
133.33
Measurement Window
1 Clock
1us
0.1s
0.1s
0.1s
-c2c jitter
-SSC
- ppm
AbsPer Short-Term Long-Term
Min Average Average
Min Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Max
9.94900
9.99900 10.00000
10.00100
7.44925
7.49925
7.50000
7.50075
1us
+SSC
Short-Term
Average
Max
1 Clock
+c2c jitter
AbsPer
Max
10.05100
7.55075
Units Notes
ns 1,2,3
ns 1,2,4
Clock Periods–Differential Outputs with Spread Spectrum Enabled
Measurement Window
SSC ON
DIF
Center
Freq.
MHz
99.75
133.00
1 Clock
-c2c jitter
AbsPer
Min
9.94906
7.44930
1us
-SSC
Short-Term
Average
Min
9.99906
7.49930
0.1s
- ppm
Long-Term
Average
Min
10.02406
7.51805
0.1s
0 ppm
Period
Nominal
10.02506
7.51880
0.1s
+ ppm
Long-Term
Average
Max
10.02607
7.51955
1us
+SSC
Short-Term
Average
Max
10.05107
7.53830
1 Clock
+c2c jitter
AbsPer
Max
10.10107
7.58830
Units Notes
ns 1,2,3
ns 1,2,4
Notes:
1 Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ/CK410B+
accuracy requirements (+/-100ppm). The 9ZXL1950 itself does not contribute to ppm error.
3 Driven by SRC output of main clock, 100 MHz PLL Mode or Bypass mode
4 Driven by CPU output of main clock, 133 MHz PLL Mode or Bypass mode
REVISION E 11/20/15
7 19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS

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9ZXL1950

19-output DB1900Z Low-Power Derivative

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