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PDF STIPN1M50-H Data sheet ( Hoja de datos )

Número de pieza STIPN1M50-H
Descripción SLLIMM-nano small low-loss intelligent molded module
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



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STIPN1M50-H
SLLIMM™-nano small low-loss intelligent molded module
IPM, 3-phase inverter, 1 A, 3.6 Ω max., 500 V MOSFET
Datasheet - production data
Applications
3-phase inverters for small power motor
drives
Dish washers, refrigerator compressors,
heating systems, air-conditioning fans,
draining and recirculation pumps
Description
Features
IPM 1 A, 500 V, RDS(on)= 3.6 Ω, 3-phase
MOSFET inverter bridge including control
ICs for gate driving
Optimized for low electromagnetic
interference
3.3 V, 5 V, 15 V CMOS/TTL input
comparators with hysteresis and pull-
down/pull-up resistors
Undervoltage lockout
Internal bootstrap diode
Interlocking function
Smart shutdown function
Comparator for fault protection against
overtemperature and overcurrent
Op-amp for advanced current sensing
Optimized pinout for easy board layout
Up to ±2 kV ESD protection (HBM
C = 100 pF, R = 1.5 kΩ)
This SLLIMM (small low-loss intelligent molded
module) nano provides a compact, high
performance AC motor drive in a simple, rugged
design. It is composed of six MOSFETs and three
half-bridge HVICs for gate driving, providing low
electromagnetic interference (EMI) characteristics
with optimized switching speed. The package is
optimized for thermal performance and
compactness in built-in motor applications, or
other low power applications where assembly
space is limited. This IPM includes an operational
amplifier, completely uncommitted, and a
comparator that can be used to design a fast and
efficient protection circuit. SLLIMM™ is a
trademark of STMicroelectronics.
Table 1: Device summary
Order code
Marking
Package
Packing
STIPN1M50-H
IPN1M50-H
NDIP-26L
Tube
February 2017
DocID030075 Rev 2
This is information on a product in full production.
1/21
www.st.com

1 page




STIPN1M50-H pdf
STIPN1M50-H
PIN26
Internal schematic diagram and pin configuration
Figure 2: Pin layout (top view)
(*) (*)
PIN17
PIN #1 ID
PIN1
(*) Dummy pin internally connected to P (positive DC input).
PIN16
AM09368V1
DocID030075 Rev 2
5/21

5 Page





STIPN1M50-H arduino
STIPN1M50-H
Condition
Shutdown enable half-bridge tri-state
Interlocking half-bridge tri-state
0 “logic state” half-bridge tri-state
1 “logic state” low-side direct driving
1 “logic state” high-side direct driving
Table 14: Truth table
Electrical characteristics
Logic input (VI)
Output
���̅���̅���̅̅���/OD
LIN HIN LVG HVG
L
X(1)
X(1)
L
L
H
HH L
L
H
LLL
L
H
HLH
L
H
LHL
H
Notes:
(1)X: don’t care.
3.3 Waveform definitions
Figure 5: Dead time and interlocking waveform definitions
DocID030075 Rev 2
11/21

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