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PDF CY7C43686AV-10AI Data sheet ( Hoja de datos )
| Número de pieza | CY7C43686AV-10AI | |
| Descripción | 3.3V 1K 4K 16K x 36 x 18 x 2 Tri Bus FIFO | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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3686AV
CY7C43646AV
CY7C43666AV
CY7C43686AV
3.3V 1K/4K/16K x36/x18x2 Tri Bus FIFO
Features
• 3.3V high-speed, low-power, First-In First-Out (FIFO)
memories with three independent ports (one bidirec-
tional ×36, and two unidirectional ×18)
• 1K ×36/×18×2 (CY7C43646AV)
• 4K ×36/×18×2 (CY7C43666AV)
• 16K ×36/×18×2 (CY7C43686AV)
• 0.25-micron CMOS for optimum speed/power
• High-speed 133-MHz operation (7.5-ns Read/Write
cycle times)
• Low power
— ICC= 60 mA
— ISB= 10 mA
• Fully asynchronous and simultaneous Read and Write
operation permitted
• Mailbox bypass register for each FIFO
• Parallel and serial programmable Almost Full and
Almost Empty flags
• Retransmit function
• Standard or FWFT user-selectable mode
• Partial and master reset
• Big or Little Endian format for word or byte bus sizes
• 128-pin TQFP packaging
• Easily expandable in width and depth
Logic Block Diagram
CLKA
CSA
W/RA
ENA
MBA
RT2
MRS1
PRS1
FFA/IRA
AFA
SPM
FS0/SD
FS1/SEN
A0–35
EFA/ORA
AEA
Port A
Control
Logic
FIFO1,
Mail1
Reset
Logic
MBF2
Mail1
Register
1K/4K/16K
× 36
Dual Ported
Memory
(FIFO1)
Write
Pointer
Read
Pointer
Status
Flag Logic
Programmable
Flag Offset
Registers
Timing
Mode
Status
Flag Logic
Read
Pointer
1
Pointer
1K/4K/16K
× 36
Dual Ported
Memory
(FIFO2)
Mail2
Register
MBF1
Port B
Control
Logic
B0–17
CLKB
RENB
CSB
SIZEB
MBB
RTI
Common
Port Logic
(B and C)
FIFO2,
Mail2
Reset
Logic
Port C
Control
Logic
EFB/ORB
AEB
BE/FWFT
FFC/IRC
AFC
MRS2
PRS2
C0–17
CLKC
WENC
SIZEC
MBC
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06026 Rev. *C
Revised December 26, 2002
1 page  
CY7C43646AV
CY7C43666AV
CY7C43686AV
Pin Definitions (continued)
Signal Name Description I/O
Function
FFA/IRA
Port A Full/Input
Ready Flag
O This is a dual-function pin. In the CY Standard mode, the FFA function is selected.
FFA indicates whether or not the FIFO1 memory is full. In the FWFT mode, the IRA
function is selected. IRA indicates whether or not there is space available for writing to
the FIFO1 memory. FFA/IRA is synchronized to the LOW-to-HIGH transition of CLKA.
FFC/IRC
Port C Full/Input
Ready Flag
O This is a dual-function pin. In the CY Standard mode, the FFC function is selected.
FFC indicates whether or not the FIFO2 memory is full. In the FWFT mode, the IRC
function is selected. IRC indicates whether or not there is space available for writing to
the FIFO2 memory. FFC/IRC is synchronized to the LOW-to-HIGH transition of CLKC.
FS1/SEN
FS0/SD
Flag Offset
Select 1/Serial
Enable
Flag Offset
Select 0/Serial
Data
I FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register
programming. During Master Reset, FS1/SEN and FS0/SD, together with SPM, select
the flag offset programming method. Three offset register programming methods are
I
available: automatically load one of three preset values (8, 16, or 64), parallel load from
Port A, and serial load. When serial load is selected for flag offset register programming,
FS1/SEN is used as an enable synchronous to the LOW-to-HIGH transition of CLKA.
When FS1/SEN is LOW, a rising edge on CLKA loads the bit present on FS0/SD into
the X and Y registers. The number of bit Writes required to program the offset registers
is 40 for the CY7C43646AV, 48 for the CY7C43666AV, and 56 for the CY7C43686AV.
The first bit Write stores the Y-register MSB and the last bit Write stores the X-register
LSB.
MBA
Port A Mailbox
Select
I A HIGH level on MBA chooses a mailbox register for Read or Write operation on Port
A. When a Read operation is performed on Port A, a HIGH level on MBA selects data
from the Mail2 register for output and a LOW level selects FIFO2 output register data
for output. When writing data into Port A, a HIGH level on MBA will write the data into
Mail1 register and a LOW will write into FIFO1.
MBB
Port B Mailbox
Select
I When a Read operation is performed on Port B, a HIGH level on MBB selects data
from the Mail1 register for output and a LOW level selects FIFO1 output register data
for output.
MBC
Port C Mailbox
Select
I When writing data into Port C, a HIGH level on MBC will write the data into Mail2
register and a LOW will write into FIFO2.
MBF1
Mail1 Register
Flag
O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the Mail1
register. Writes to the Mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH
by a LOW-to-HIGH transition of CLKB when a Port B Read is selected and MBB is HIGH.
MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.
MBF2
Mail2 Register
Flag
O MBF2 is set LOW by a LOW-to-HIGH transition of CLKC that writes data to the Mail2
register. Writes to the Mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH
by a LOW-to-HIGH transition of CLKA when a Port A Read is selected and MBA is HIGH.
MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.
MRS1
FIFO1 Master
Reset
I A LOW on this pin initializes the FIFO1 Read and Write pointers to the first location
of memory and sets the Port B output register to all zeroes. A LOW pulse on MRS1
selects the programming method (serial or parallel) and one of three programmable flag
default offsets for FIFO1. It also configures Port B for bus size and endian arrangement.
Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB
must occur while MRS1 is LOW.
MRS2
FIFO2 Master
Reset
I A LOW on this pin initializes the FIFO2 Read and Write pointers to the first location
of memory and sets the Port A output register to all zeroes. A LOW pulse on MRS2
selects one of three programmable flag default offsets for FIFO2. Four LOW-to-HIGH
transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS2
is LOW.
PRS1
FIFO1 Partial
Reset
I A LOW on this pin initializes the FIFO1 Read and Write pointers to the first location
of memory and sets the Port B output register to all zeroes. During Partial Reset,
the currently selected bus size, endian arrangement, programming method (serial or
parallel), and programmable flag settings are all retained.
Document #: 38-06026 Rev. *C
Page 5 of 40
5 Page 
CY7C43646AV
CY7C43666AV
CY7C43686AV
.
PORT B BUS SIZING
BYTE ORDER ON PORT A:
A27–35
A
A18–26
B
A9–17
C
A0–8
D
Write to FIFO1
BE SIZEB
HL
BE SIZEB
LL
BE SIZEB
HH
BE SIZEB
LH
B9–17
A
B9–17
C
B0–8
B
B0–8
D
1st: Read from
FIFO1
2nd: Read from FIFO1
(A) WORD SIZE - BIG ENDIAN
B9–17
C
B9–17
A
B0–8
D
B0–8
B
1st: Read from FIFO1
2nd: Read from FIFO1
(B) WORD SIZE - LITTLE ENDIAN
B9–17
B0–8
A
1st: Read from FIFO1
B9–17
B0–8
B
2nd: Read from FIFO1
B9–17
B0–8
C
3rd: Read from FIFO1
B9–17
B0–8
D
4th: Read from FIFO1
(C) BYTE SIZE - BIG ENDIAN
B9–17
B9–17
B9–17
B9–17
B0–8
D
B0–8
C
B0–8
B
B0–8
A
1st: Read from FIFO1
2nd: Read from FIFO1
3rd: Read from FIFO1
4th: Read from FIFO1
(D) BYTE SIZE - LITTLE ENDIAN
Document #: 38-06026 Rev. *C
Page 11 of 40
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CY7C43686AV-10AI.PDF ] | |
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