PDF CY7C460A-15JC Data sheet ( Hoja de datos )

Número de pieza	CY7C460A-15JC
Descripción	Asynchronous/ Cascadable 8K/16K/32K/64K x9 FIFOs
Fabricantes	Cypress Semiconductor
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No Preview Available ! 60A CY7C460A/CY7C462A CY7C464A/CY7C466A Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs Features Functional Description • High-speed, low-power, first-in first-out (FIFO) memories • 8K x 9 FIFO (CY7C460A) • 16K x 9 FIFO (CY7C462A) • 32K x 9 FIFO (CY7C464A) • 64K x 9 FIFO (CY7C466A) • 10-ns access times, 20-ns read/write cycle times • High-speed 50-MHz read/write independent of depth/width • Low operating power — ICC= 60 mA — ISB =8 mA • Asynchronous read/write • Empty and Full flags • Half Full flag (in standalone mode) • Retransmit (in standalone mode) • TTL-compatible • Width and Depth Expansion Capability • 5V ± 10% supply • PLCC, LCC, 300-mil and 600-mil DIP packaging • Three-state outputs • Pin compatible density upgrade to CY7C42X/46X family • Pin compatible and functionally equivalent to IDT7205, IDT7206, IDT7207, IDT7208 The CY7C460A, CY7C462A, CY7C464A, and CY7C466A are respectively, 8K, 16K, 32K, and 64K words by 9-bit wide first-in first-out (FIFO) memories. Each FIFO memory is organized such that the data is read in the same sequential order that it was written. Full and Empty flags are provided to prevent over- run and underrun. Three additional pins are also provided to facilitate unlimited expansion in width, depth, or both. The depth expansion technique steers the control signals from one device to another by passing tokens. The read and write operations may be asynchronous; each can occur at a rate of up to 50 MHz. The write operation occurs when the Write (W) signal is LOW. Read occurs when Read (R) goes LOW. The nine data outputs go to the high-imped- ance state when R is HIGH. A Half Full (HF) output flag is provided that is valid in the stan- dalone (single device) and width expansion configurations. In the depth expansion configuration, this pin provides the ex- pansion out (XO) information that is used to tell the next FIFO that it will be activated. In the standalone and width expansion configurations, a LOW on the Retransmit (RT) input causes the FIFOs to retransmit the data. Read Enable (R) and Write Enable (W) must both be HIGH during a retransmit cycle, and then R is used to access the data. The CY7C460A, CY7C462A, CY7C464A, and CY7C466A are fabricated using Cypress’s advanced 0.5µ RAM3 CMOS tech- nology. Input ESD protection is greater than 2000V and latch-up is prevented by careful layout and the use of guard rings. Logic Block Diagram DATA INPUTS (D0−D 8) W WRITE CONTROL WRITE POINTER DUAL PORT RAM ARRAY 8K x 9 16K x 9 32K x 9 64K x 9 R READ CONTROL THREE– STATE BUFFERS DATA OUTPUTS (Q0-Q 8) READ POINTER RESET LOGIC Pin Configurations PLCC/LCC Top View D2 D1 D0 XI FF Q0 Q1 NC Q2 MR FL/RT W 4 3 2 1 32 31 30 5 29 6 28 7 27 8 7C460A 7C462A 9 7C464A 10 7C466A 26 25 24 D6 D7 NC FL/RT MR EF D8 D3 D2 D1 D0 XI FF 11 23 12 22 13 21 14 15 16 17 18 19 20 XO/HF Q7 Q6 Q0 Q1 Q2 Q3 Q8 C46XA–2 GND DIP Top View 1 28 2 27 3 26 4 25 5 24 6 7C460A 7C462A 23 7 7C464A 22 8 7C466A 21 9 20 10 19 11 18 12 17 13 16 14 15 VCC D4 D5 D6 D7 FL/RT MR EF XO/HF Q7 Q6 Q5 Q4 R C46XA–3 FLAG LOGIC EF FF EXPANSION XI LOGIC XO/HF C46XA–1 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Document #: 38-06011 Rev. A Revised December 26, 2002 1 page CY7C460A/CY7C462A CY7C464A/CY7C466A Switching Waveforms[7] Asynchronous Read and Write tA R tRC tRR tPR tA Q0−Q 8 W D0−D 8 tLZR tPW tDVR DATA VALID tWC tWR tSD tHD DATA VALID tHZR DATA VALID tPW tSD tHD DATA VALID Master Reset MR R, W [9] EF HF FF tMRSC [10] tPMR tEFL tHFH tFFH tRPW tWPW tRMR C460A–7 C460A–8 Half Full Flag W R HF HALF FULL tWHF HALF FULL+1 HALF FULL tRHF C460A–9 Notes: 8. A HIGH-to-LOW transition of either the write or read strobe causes a HIGH-to-LOW transition of the responding flag. Correspondingly, a LOW-to-HIGH strobe transition causes a LOW-to-HIGH flag transition. 9. W and R = VIH around the rising edge of MR. 10. tMSRC = t PMR + t RMR Document #: 38-06011 Rev. A Page 5 of 15 5 Page CY7C460A/CY7C462A CY7C464A/CY7C466A Ordering Information (continued) 64K x 9 Asynchronous FIFO Speed (ns) Ordering Code 10 CY7C466A-10JC CY7C466A-10PC CY7C466A-10PTC CY7C466A-10JI 15 CY7C466A-15JC CY7C466A-15PC CY7C466A-15PTC CY7C466A-15LMB 25 CY7C466A-25JC CY7C466A-25PC CY7C466A-25PTC Package Name J65 P15 P21 J65 J65 P15 P21 L55 J65 P15 P21 Package Type 32-Lead Plastic Leaded Chip Carrier 28-Lead (600-Mil) Molded DIP 28-Lead (300-Mil) Molded DIP 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 28-Lead (600-Mil) Molded DIP 28-Lead (300-Mil) Molded DIP 32-Pin Rectangular Leadless Chip Carrier 32-Lead Plastic Leaded Chip Carrier 28-Lead (600-Mil) Molded DIP 28-Lead (300-Mil) Molded DIP Operating Range Commercial Industrial Commercial Military Commercial Document #: 38-06011 Rev. *A Page 11 of 15 11 Page

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