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PDF CXD3027R Data sheet ( Hoja de datos )
| Número de pieza | CXD3027R | |
| Descripción | CD Digital Signal Processor with Built-in Digital Servo + Shock-Proof Memory Controller + Digital High & Bass Boost | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXD3027R
CD Digital Signal Processor with Built-in Digital Servo +
Shock-Proof Memory Controller + Digital High & Bass Boost
Description
The CXD3027R is a digital signal processor LSI for CD
players. This LSI incorporates a digital servo, high & bass
boost, shock-proof memory controller, 1-bit DAC and
analog low-pass filter.
120 pin LQFP (Plastic)
Features
• All digital signal processing during playback is performed
with a single chip
• Highly integrated mounting possible due to a built-in RAM
Digital Signal Processor (DSP) Block
• Supports CAV (Constant Angular Velocity) playback
• Frame jitter free
• 0.5× to 4× speed continuous playback possible
• Allows relative rotational velocity readout
• Wide capture range playback mode
• Spindle rotational velocity following method
• Supports 1× to 4× speed playback
• Supports variable pitch playback
• The bit clock, which strobes the EFM signal, is generated
by the digital PLL.
• EFM data demodulation
• Enhanced EFM frame sync signal protection
• Refined super strategy-based powerful error correction
C1: double correction, C2: quadruple correction
Supported during 4× speed playback
• Noise reduction during track jumps
• Auto zero-cross mute
• Subcode demodulation and subcode-Q data error
detection
• Digital spindle servo
• 16-bit traverse counter
• Asymmetry correction circuit
• CPU interface on serial bus
• Error correction monitor signal, etc. output from a new
CPU interface
• Servo auto sequencer
• Fine search performs track jumps with high accuracy
• Digital audio interface outputs
• Digital level meter, peak meter
• Bilingual compatible
• VCO control mode
• CD TEXT data demodulation
• Digital Out can be generated from the audio serial input.
(also supported after shock-proof and digital bass boost
processing, subcode-Q addition function)
Digital Servo (DSSP) Block
• Microcomputer software-based flexible servo control
• Offset cancel function for servo error signal
• Auto gain control function for servo loop
• E:F balance, focus bias adjustment functions
• Surf jump function supporting micro two-axis
• Tracking filter: 6 stages
Focus filter: 5 stages
Shock-Proof Memory Controller Block
• Supports an external 4M-bit/16M-bit DRAM
• Time axis-based data linking
• ADPCM compression method (uncompressed/4 bits/
6 bits/8 bits)
Digital Filter, DAC and Analog Low-pass Filter Blocks
• Digital dynamic bass boost and high boost
Bass Boost: 4th-order IIR 24dB/Oct
+10dB/+14dB/+18dB/+22dB
High Boost: Second-order IIR 12dB/Oct
+4dB/+6dB/+8dB/+10dB
• Independent turnover frequency selection possible
Bass Boost: 125Hz/160Hz/200Hz
High Boost: 5kHz/7kHz
• Digital dynamics (compressor)
Volume increased by +5dB at low level
• 8× oversampling digital filter
(attenuation: 61dB, ripple within band: ±0.0075dB)
• Digital signal output possible after boost
• Serial data format selectable from (output) 20 bits/
18 bits/16 bits (rearward truncation, MSB first)
• Digital attenuation: – ∞, –60 to +6dB, 2048 steps (linear)
• Soft mute
• Digital de-emphasis
• High-cut filter
Applications
CD players
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
• Supply voltage
VDD, AVDD –0.3 to +4.6
V
• Input voltage
VI
–0.3 to +4.6
V
(VSS – 0.3V to VDD + 0.3V)
• Output voltage
VO
–0.3 to +4.6
V
• Storage temperature Tstg
–40 to +125
°C
• Supply voltage difference
AVSS – VSS –0.3 to +0.3
V
AVDD – VDD –0.3 to +0.3V (AVDD < 2.2V)
AVDD – VDD –0.3 to +1.4V (AVDD = 2.2 to 3.6V)
Recommended Operating Conditions
• Supply voltage VDD , AVDD0, 3 2.2 to 3.6
AVDD1, 2, DVDD VDD to 3.6
• Operating temperature Topr
–20 to +75
V
V
°C
I/O Pin Capacitance
• Input capacitance CI
• Output capacitance CO
Note) Measurement conditions
12 (max.)
12 (max.)
VDD = VI = 0V
fM = 1MHz
pF
pF
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E99431B04-PS
1 page  
CXD3027R
Pin
No.
Symbol
I/O
Description
32 COUT I/O 1, 0 Track count signal I/O.
33 MIRR I/O 1, 0 Mirror signal I/O.
34 DFCT I/O 1, 0 Defect signal I/O.
35 FOK
I/O 1, 0 Focus OK signal I/O.
36 PWMI I
Spindle motor external control input.
37 LOCK
I/O 1, 0
GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal.
If GFS is low eight consecutive samples, this pin outputs low.
Or input when LKIN = 1.
38 TEST1 O
Test pin.
39 TEST2 O
Test pin.
40 TEST3 O
Test pin.
41 VDD1
— — Digital power supply.
42 C176
O
176.4kHz output.
43 MDP
O 1, Z, 0 Spindle motor servo control output.
44 MDS
O
Spindle motor servo control output.
45 SSTP
I
Disc innermost track detection signal input.
46 SFDR O 1, 0 Sled drive output.
47 SRDR O 1, 0 Sled drive output.
48 TFDR O 1, 0 Tracking drive output.
49 TRDR O 1, 0 Tracking drive output.
50 FFDR O 1, 0 Focus drive output.
51 FRDR O 1, 0 Focus drive output.
52 VSS1
— — Digital GND.
53 TEST
I
Test pin. Normally, GND.
54 TES1
I
Test pin. Normally, GND.
55 AVDD0 — — Analog power supply.
56 IGEN
I
Operational amplifier constant current input.
57 AVSS0 — — Analog GND.
58 RFDC I
RF signal input.
59 CE
I
Center servo analog input or E input.
60 TE
I
Tracking error signal input or F input.
61 SE
I
Sled error signal input or B input.
62 FE
I
Focus error signal input or A output.
63 VC
I
Center voltage input.
64 VPCO O 1, Z, 0 Wide-band EFM PLL charge pump output.
65 VCTL
I
Wide-band EFM PLL VCO2 control voltage input.
–5–
5 Page 
(2) CLOK, DATA, XLAT, SQCK and EXCK pins
(VDD = AVDD = 3.3 ± 0.3V, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item Symbol Min. Typ. Max. Unit
Clock frequency
Clock pulse width
Setup time
Hold time
Delay time
Latch pulse width
fCK
tWCK
tSU
tH
tD
tWL
750
300
300
300
750
0.65 MHz
ns
ns
ns
ns
ns
EXCK SQCK frequency
fT
EXCK SQCK pulse width
tWT
COUT frequency (during input)∗ fT
COUT pulse width (during input)∗ tWT
∗ Only when $44 and $45 are executed.
750
7.5
0.65 MHz
ns
65 kHz
µs
CLOK
1/fCK
tWCK
tWCK
DATA
XLAT
tSU tH
tD tWL
EXCK
SQCK
COUT
tWT tWT
1/fT
SBSO
SQSO
tSU tH
CXD3027R
– 11 –
11 Page | ||
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| PDF Descargar | [ Datasheet CXD3027R.PDF ] | |
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