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PDF 3X38FTR Data sheet ( Hoja de datos )
| Número de pieza | 3X38FTR | |
| Descripción | OCTAL-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX | |
| Fabricantes | Agere Systems | |
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Preliminary Data Sheet
September 2000
3X38FTR 208-Pin SQFP
OCTAL-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX
Overview
The 3X38FTR 208-Pin SQFP is an eight-channel,
single-chip complete transceiver designed specifi-
cally for dual-speed 10Base-T, 100Base-TX, and
100Base-FX switches and repeaters. It supports
simultaneous operation in three separate IEEE *
standard modes: 10Base-T, 100Base-TX, and
100Base-FX. The 3X38 uses 0.25 µm low-power
CMOS to achieve extremely low power dissipation
and operates from a single 3.3 V power supply.
Each channel implements the following:
s 10Base-T transceiver function of IEEE 802.3.
s 100Base-TX transceiver function of IEEE 802.3u.
s 100Base-FX transceiver function of IEEE 802.3u.
s Autonegotiation of IEEE 802.3u.
s MII management of IEEE 802.3u.
The 3X38 supports operations over two pairs of
unshielded twisted-pair (UTP) cable (10Base-T and
100Base-TX) and over fiber-optic cable (100Base-
FX).
It has been designed with a flexible system interface
that allows configuration for optimum performance
and effortless design. The individual per-port system
interface can be configured as 10 Mbits/s, or
100 Mbits/s reduced MII (RMII), or 10 Mbits/s, or
100 Mbits/s serial MII (SMII).
Features
10 Mbits/s Transceiver
s Compatible with IEEE 802.3 10Base-T standard
for category 3 unshielded twisted-pair (UTP) cable.
s Compatible with the reduced MII (RMII) specifica-
tion of the RMII consortium version 1.2.
s Selectable 7-pin RMII or 2-pin serial MII (SMII).
s Autopolarity detection and correction.
s Adjustable squelch level for extended line length
capability (two levels).
s On-chip filtering eliminates the need for external
filters.
s Half- and full-duplex operations.
100 Mbits/s TX Transceiver
s Compatible with IEEE 802.3u PCS (clause 23),
PMA (clause 24), autonegotiation (clause 28), and
PMD (clause 25) specifications.
s Compatible with the reduced MII (RMII) specifica-
tion of the RMII consortium version 1.2.
s Selectable 7-pin RMII, 2-pin SMII (serial MII).
s Scrambler/descrambler bypass.
s Selectable carrier sense signal generation (CRS)
asserted during either transmission or reception in
half duplex (CRS asserted during reception only in
full duplex).
s Full- or half-duplex operations.
s On-chip filtering and adaptive equalization that
eliminates the need for external filters.
100 Mbits/s FX Transceiver
s Pseudo-ECL compatible input/output for 100Base-
FX support (with fiber-optic signal detect).
s Compatible with IEEE 802.3u 100Base-FX stan-
dard.
s Reuses existing twisted-pair I/O pins for compati-
ble fiber-optic transceiver pseudo-ECL (PECL)
data:
— No additional data pins required.
— Reuses existing 3X38 pins for fiber-optic
signal detect (FOSD) inputs.
* IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
1 page  
Preliminary Data Sheet
September 2000
3X38FTR 208-Pin SQFP
OCTAL-FET for 10Base-T/100Base-TX/FX
Description
RMII Mode
The reduced media independent interface (RMII) is a
low pin count interface specification promulgated by the
RMII consortium. This specification reduces the total
number of pins from 16 for the IEEE 802.3U MII inter-
face to seven for the RMII. Architecturally, the RMII
specification provides for an additional reconciliation
sublayer on either side of the MII but, in the 3X38, has
been implemented in the absence of the MII.
The management interface (MDIO/MDC) remains iden-
tical to that defined in IEEE 802.3u.
The RMII specification has the following characteris-
tics:
s It supports 10 Mbits/s and 100 Mbits/s data rates.
s A single 50 MHz clock reference is sourced from
MAC to PHY or from an external shared source.
s It provides independent 2-bit wide transmit and
receive data paths.
SMII Mode
The serial media independent interface (SMII) is a low
pin count interface specification promulgated by
Cisco*. This specification reduces the total number of
pins from 16 for the IEEE 802.3u MII interface to two for
the SMII. Architecturally, the SMII specification pro-
vides for an additional reconciliation sublayer on either
side of the MII but, in the 3X38, has been implemented
in the absence of the MII.
The management interface (MDIO/MDC) remains iden-
tical to that defined in IEEE 802.3u.
The SMII specification has the following characteristics:
s It supports 10 Mbits/s and 100 Mbits/s data rates.
s A single 125 MHz clock reference is sourced from
MAC to PHY or from an external shared source.
s It provides independent serial transmit and receive
data paths.
LED Control
LEDs can be accessed in one of the following modes:
s Serial mode. In this mode, all of the LEDs are time-
division multiplexed onto one pin, with a second pin
acting as the clock and a third as a strobe. All LEDs
and all channels share the same pins.
s Parallel mode. In this mode, each LED and each
channel has its own pin. There is a total of four LED
pins per channel for a total of 32 pins.
s Bicolor mode. In this mode, each channel has two
outputs to control a bicolor LED. One LED can be
used for each port, indicating link and activity.
In all modes, the LEDs can be operated as
follows:
s LED stretch.
s LED blink.
s No stretch or blink.
Clocking
The 3X38 operates with a 50 MHz clock input when in
the RMII mode, and with a 125 MHz clock input when
in the SMII mode.
FX Mode
Each individual port of the 3X38 can be operated in
100Base-FX mode by selecting it through the pin pro-
gram option (FX_MODE_EN[7:0]), or through the reg-
ister bit (register 29, bit 0).
When operating in FX mode, the twisted-pair I/O pins
are reused as the fiber-optic transceiver I/O data pins,
and the fiber-optic signal detect (FOSD) inputs are
enabled.
When a port is placed in FX mode, it will automatically
configure the port for 100Base-FX operation (and the
register bit control will be ignored) such that:
s The far-end fault signaling option will be enabled.
s The MLT-3 encoding/decoding will be disabled.
s Scrambler/descrambler will be disabled.
s Autonegotiation will be disabled.
s The signal detect inputs will be activated.
s 10Base-T will be disabled.
Lucent Technologies Inc.
* Cisco is a registered trademark of Cisco Systems.
5
5 Page 
Preliminary Data Sheet
September 2000
Pin Information (continued)
Pin Diagram for SMII Mode
3X38FTR 208-Pin SQFP
OCTAL-FET for 10Base-T/100Base-TX/FX
VSS
ACTLED_5/BIACTLED_5/CARIN_EN
ACTLED_4/BIACTLED_4/AUTO_EN
ACTLED_3/BIACTLED_3/SCRAM_DESC_BYPASS
ACTLED_2/BIACTLED_2/LITF_EN
ACTLED_1/BIACTLED_1/BLINK_LED_MODE
ACTLED_0/BIACTLED_0/STRETCH_LED
NC
NC
STXD_7
NC
NC
NC
STXD_6
VDD
NC
NC
NC
SRXD_7
NC
NC
SRXD_6
NC
STXD_5
SSYNC_7:4
NC
NC
SRXD_5
STXD_4
VDD
NC
NC
SRXD_4
NC
NC
NC
STXD_3
NC
NC
NC
SRXD_3
NC
NC
STXD_2
VDD
NC
NC
SRXD_2
SSYNC_3:0
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51 SMII MODE
52
3X38FTR 208-PIN SQFP
Figure 6. 3X38 Pinout for SMII Mode
156
VDDA
155 TPIN+7/FOIN+7
154 TPIN–7/FOIN–7
153
VDDA
152 TPIN+6/FOIN+6
151 TPIN–6/FOIN–6
150
VDDA
149 TPIN+5/FOIN+5
148 TPIN–5/FOIN–5
147
VDDA
146 TPIN+4/FOIN+4
145 TPIN–4/FOIN–4
144 VSS
143
VDDA
142 TPIN+3/FOIN+3
141 TPIN–3/FOIN–3
140
VDDA
139 TPIN+2/FOIN+2
138 TPIN–2/FOIN–2
137
VDDA
136 TPIN+1/FOIN+1
135 TPIN–1/FOIN–1
134 VSS
133
VDDA
132 TPIN+0/FOIN+0
131 TPIN–0/FOIN–0
130 VSS
129 REXTBS
128
VDDA
127
VDDPLL
126 RMCLK
125 VSS
124
VDDA
123 REXT100
122 REXT10
121 VSS
120 TPOUT–7/FOOUT–7
119 TPOUT+7/FOOUT+7
118 TPOUT–6/FOOUT–6
117 TPOUT+6/FOOUT+6
116 TPOUT–5/FOOUT–5
115 TPOUT+5/FOOUT+5
114 TPOUT–4/FOOUT–4
113 TPOUT+4/FOOUT+4
112 TPOUT–3/FOOUT–3
111 TPOUT+3/FOOUT+3
110 TPOUT–2/FOOUT–2
109 TPOUT+2/FOOUT+2
108 TPOUT–1/FOOUT–1
107 TPOUT+1/FOOUT+1
106 TPOUT–0/FOOUT–0
105 TPOUT+0/FOOUT+0
5-8124(F).r1
Lucent Technologies Inc.
11
11 Page | ||
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| PDF Descargar | [ Datasheet 3X38FTR.PDF ] | |
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