|
|
PDF DS92LV1023 Data sheet ( Hoja de datos )
| Número de pieza | DS92LV1023 | |
| Descripción | 40-66 MHz 10 Bit Bus LVDS Serializer and Deserializer | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de DS92LV1023 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
|
No Preview Available !
June 2002
DS92LV1023 and DS92LV1224
40-66 MHz 10 Bit Bus LVDS Serializer and Deserializer
General Description
The DS92LV1023 transforms a 10-bit wide parallel
LVCMOS/LVTTL data bus into a single high speed Bus
LVDS serial data stream with embedded clock. The
DS92LV1224 receives the Bus LVDS serial data stream and
transforms it back into a 10-bit wide parallel data bus and
recovers parallel clock. The DS92LV1023 transmits data
over backplanes or cable. The single differential pair data
path makes PCB design easier. In addition, the reduced
cable, PCB trace count, and connector size tremendously
reduce cost. Since one output transmits clock and data bits
serially, it eliminates clock-to-data and data-to-data skew.
The powerdown pin saves power by reducing supply current
when not using either device. Upon power up of the Serial-
izer, you can choose to activate synchronization mode or
allow the Deserializer to use the
synchronization-to-random-data feature. By using the syn-
chronization mode, the Deserializer will establish lock to a
signal within specified lock times. In addition, the embedded
clock guarantees a transition on the bus every 12-bit cycle.
This eliminates transmission errors due to charged cable
conditions. Furthermore, you may put the DS92LV1023 out-
put pins into TRI-STATE ® to achieve a high impedance
state. The PLL can lock to frequencies between 40 MHz and
66 MHz.
Features
n Clock recovery from PLL lock to random data patterns.
n Guaranteed transition every data transfer cycle
n Chipset (Tx + Rx) power consumption < 500 mW (typ)
@ 66 MHz
n Single differential pair eliminates multi-channel skew
n Flow-through pinout for easy PCB layout
n 660 Mbps serial Bus LVDS data rate (at 66 MHz clock)
n 10-bit parallel interface for 1 byte data plus 2 control bits
n Synchronization mode and LOCK indicator
n Programmable edge trigger on clock
n High impedance on receiver inputs when power is off
n Bus LVDS serial output rated for 27Ω load
n Small 28-lead SSOP package
Block Diagrams
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2002 National Semiconductor Corporation DS100933
10093301
www.national.com
1 page  
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)
LVCMOS/LVTTL Input
−0.3V to +4V
Voltage
LVCMOS/LVTTL Output
−0.3V to (VCC +0.3V)
Voltage
−0.3V to (VCC +0.3V)
Bus LVDS Receiver Input
Voltage
−0.3V to +3.9V
Bus LVDS Driver Output
Voltage
−0.3V to +3.9V
Bus LVDS Output Short
Circuit Duration
10mS
Junction Temperature
+150˚C
Storage Temperature
−65˚C to +150˚C
Lead Temperature
(Soldering, 4 seconds)
+260˚C
Maximum Package Power Dissipation Capacity
@ 25˚C Package:
28L SSOP
1.27 W
Package Derating:
10.3 mW/˚C above
28L SSOP
+25˚C
θja
θjc
ESD Rating for
DS92LV1023
HBM (1.5kOhm, 100pF)
MM
ESD Rating for
DS92LV1224
HBM (1.5kOhm, 100pF)
MM
97˚C/W
27˚C/W
>1kV
> 250V
>2kV
> 250V
Recommended Operating
Conditions
Supply Voltage (VCC)
Operating Free Air
Temperature (TA)
Receiver Input Range
Supply Noise Voltage
(VCC)
Min Nom Max Units
3.0 3.3 3.6 V
−40 +25 +85 ˚C
0 2.4 V
100 mVP-P
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min Typ Max Units
SERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (apply to DIN0-9, TCLK, PWRDN, TCLK_R/F, SYNC1, SYNC2, DEN)
VIH High Level Input Voltage
2.0
VCC
V
VIL Low Level Input Voltage
GND
0.8 V
VCL Input Clamp Voltage
IIN Input Current
ICL = −18 mA
VIN = 0V or 3.6V
-0.86 −1.5
−10 ±1 +10
V
µA
DESERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (apply to pins PWRDN, RCLK_R/ F, REN, REFCLK = inputs; apply
to pins ROUT, RCLK, LOCK = outputs)
VIH High Level Input Voltage
VIL Low Level Input Voltage
VCL Input Clamp Voltage
ICL = −18 mA
IIN Input Current
VIN = 0V or 3.6V
VOH High Level Output Voltage
IOH = −9 mA
VOL Low Level Output Voltage
IOL = 9 mA
IOS Output Short Circuit Current VOUT = 0V
IOZ TRI-STATE Output Current
PWRDN or REN = 0.8V, VOUT = 0V or VCC
SERIALIZER Bus LVDS DC SPECIFICATIONS (apply to pins DO+ and DO−)
2.0
GND
−10
2.2
GND
−15
−10
−0.62
±1
3.0
0.25
−47
±0.1
VCC
0.8
−1.5
+15
VCC
0.5
−85
+10
V
V
V
µA
V
V
mA
µA
VOD Output Differential Voltage
(DO+)–(DO−)
RL = 27Ω, Figure 18
200 290
mV
∆VOD
Output Differential Voltage
Unbalance
35 mV
VOS
∆VOS
Offset Voltage
Offset Voltage Unbalance
1.05 1.1 1.3
V
4.8 35 mV
5 www.national.com
5 Page 
AC Timing Diagrams and Test Circuits (Continued)
FIGURE 10. SYNC Timing Delays
10093323
FIGURE 11. Serializer Delay
10093311
FIGURE 12. Deserializer Delay
11
10093312
www.national.com
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet DS92LV1023.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| DS92LV1021 | 16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer | National Semiconductor |
| DS92LV1021 | DS92LV1021 and DS92LV1210 16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer (Rev. C) |  Texas Instruments |
| DS92LV1021A | 16-40 MHz 10 Bit Bus LVDS Serializer | National Semiconductor |
| DS92LV1021A | DS92LV1021A 16-40 MHz 10 Bit Bus LVDS Serializer (Rev. G) | Texas Instruments |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |