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4X16E83V 데이터시트 PDF




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부품번호 4X16E83V 기능
기능 4 MEG x 16 EDO DRAM
제조업체 ETC
로고 ETC 로고


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4X16E83V 데이터시트, 핀배열, 회로
EDO DRAM
4 MEG x 16
EDO DRAM
4X16E43V
FEATURES
• Single +3.3V ±0.3V power supply
• Industry-standard x16 pinout, timing, functions,
and package
• 12 row, 10 column addresses (4)
13 row, 9 column addresses (8)
• High-performance CMOS silicon-gate process
• All inputs, outputs and clocks are LVTTL-compatible
• Extended Data-Out (EDO) PAGE MODE access
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH
distributed across 64ms
• Self refresh for low-power data retention
OPTIONS
• Plastic Package
50-pin TSOP (400 mil)
• Timing
50ns access
60ns access
• Refresh Rates
4K
8K
MARKING
TW
-5
-6
4
8
• Operating Temperature Range
Commercial (0°C to +70°C)
Extended (-40°C to +85°C)
None
IT
NOTE: 1. The “#” symbol indicates signal is active LOW.
PIN ASSIGNMENT (Top View)
50-Pin TSOP
VCC
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
NC
VCC
WE#
RAS#
NC
NC
NC
NC
A0
A1
A2
A3
A4
A5
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50 VSS
49 DQ15
48 DQ14
47 DQ13
46 DQ12
45 VSS
44 DQ11
43 DQ10
42 DQ9
41 DQ8
40 NC
39 VSS
38 CASL#
37 CASH#
36 OE#
35 NC
34 NC
33 NC/A12
32 A11
31 A10
30 A9
29 A8
28 A7
27 A6
26 VSS
A12 for "8K" version, NC for "4K" version.
Configuration
Refresh
Row Address
Column Addressing
4X16E43V
4 Meg x 16
4K
4K (A0-A11)
1K (A0-A9)
4X16E83V
4 Meg x 16
8K
8K (A0-A12)
512 (A0-A8)
Part Number Example:
MEM4X16E43VTW-5
KEY TIMING PARAMETERS
SPEED
-5
-6
tRC
84ns
104ns
tRAC
50ns
60ns
tPC
20ns
25ns
tAA
25ns
30ns
tCAC
13ns
15ns
tCAS
8ns
10ns
4 MEG x 16 EDO DRAM PART NUMBERS
PART NUMBER
4X16E43VTW-x
4X16E83VTW-x
x = speed
REFRESH
ADDRESSING
4
8
PACKAGE
400-TSOP
400-TSOP
1




4X16E83V pdf, 반도체, 판매, 대치품
DRAM ACCESS (continued)
the upper byte (DQ8-DQ15). General byte and word
access timing is shown in Figures 1 and 2.
A logic HIGH on WE# dictates read mode, while a
logic LOW on WE# dictates write mode. During a
WRITE cycle, data-in (D) is latched by the falling edge
of WE or CAS# (CASL# or CASH#), whichever occurs
last. An EARLY WRITE occurs when WE is taken LOW
prior to either CAS# falling. A LATE WRITE or READ-
MODIFY-WRITE occurs when WE falls after CAS# (CASL#
or CASH#) is taken LOW. During EARLY WRITE cycles,
the data outputs (Q) will remain High-Z, regardless of
the state of OE#. During LATE WRITE or READ-MODIFY-
WRITE cycles, OE# must be taken HIGH to disable the
data outputs prior to applying input data. If a LATE
WRITE or READ-MODIFY-WRITE is attempted while
keeping OE# LOW, no write will occur, and the data
outputs will drive read data from the accessed location.
Additionally, both bytes must always be of the same
mode of operation if both bytes are active. A CAS#
precharge must be satisfied prior to changing modes of
operation between the upper and lower bytes. For
example, an EARLY WRITE on one byte and a LATE
4 MEG x 16
EDO DRAM
WRITE on the other byte are not allowed during the
same cycle. However, an EARLY WRITE on one byte and
a LATE WRITE on the other byte, after a CAS# precharge
has been satisfied, are permissible.
EDO PAGE MODE
DRAM READ cycles have traditionally turned the
output buffers off (High-Z) with the rising edge of
CAS#. If CAS# went HIGH and OE# was LOW (active),
the output buffers would be disabled. The 64Mb EDO
DRAM offers an accelerated page mode cycle by elimi-
nating output disable from CAS# HIGH. This option is
called EDO, and it allows CAS# precharge time (tCP) to
occur without the output data going invalid (see READ
and EDO-PAGE-MODE READ waveforms).
EDO operates like any DRAM READ or FAST-PAGE-
MODE READ, except data is held valid after CAS# goes
HIGH, as long as RAS# and OE# are held LOW and WE#
is held HIGH. OE# can be brought LOW or HIGH while
CAS# and RAS# are LOW, and the DQs will transition
between valid data and High-Z. Using OE#, there are
RAS#
WORD READ
LOWER BYTE READ
CASL#
CASH#
WE#
LOWER BYTE
(DQ0-DQ7)
OF WORD
UPPER BYTE
(DQ8-DQ15)
OF WORD
STORED
DATA
1
1
0
1
1
1
1
1
OUTPUT
DATA
1
1
0
1
1
1
1
1
OUTPUT
DATA
1
1
0
1
1
1
1
1
STORED
DATA
1
1
0
1
1
1
1
1
STORED
DATA
1
1
0
1
1
1
1
1
0Z
1Z
0Z
1Z
0Z
0Z
0Z
0Z
0 00
1 11
0 00
1 11
0 00
0 00
0 00
0 00
OUTPUT
DATA
1
1
0
1
1
1
1
1
OUTPUT
DATA
1
1
0
1
1
1
1
1
STORED
DATA
1
1
0
1
1
1
1
1
ZZ0
ZZ1
ZZ0
ZZ1
ZZ0
ZZ0
ZZ0
ZZ0
Z = High-Z
ADDRESS 0
ADDRESS 1
Figure 2
WORD and BYTE READ Example
4

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4X16E83V 전자부품, 판매, 대치품
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Relative to VSS ................ -1V to +4.6V
Voltage on NC, Inputs or I/O Pins
Relative to VSS ....................................... -1V to +4.6V
Operating Temperature, TA (ambient)
Commercial ......................................... 0°C to +70°C
Extended (IT) ................................. -40°C to +85°C**
Storage Temperature (plastic) ............ -55°C to +150°C
Power Dissipation ................................................... 1W
4 MEG x 16
EDO DRAM
*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Note: 1) (VCC = +3.3V ±0.3V)
PARAMETER/CONDITION
SUPPLY VOLTAGE
INPUT HIGH VOLTAGE:
Valid Logic 1; All inputs, I/Os and any NC
INPUT LOW VOLTAGE:
Valid Logic 0; All inputs, I/Os and any NC
INPUT LEAKAGE CURRENT:
Any input at VIN (0V <_ VIN <_ VCC + 0.3V);
All other pins not under test = 0V
OUTPUT HIGH VOLTAGE:
IOUT = -2mA
OUTPUT LOW VOLTAGE:
IOUT = 2mA
OUTPUT LEAKAGE CURRENT:
Any output at VOUT (0V <_ VOUT <_ VCC + 0.3V);
DQ is disabled and in High-Z state
SYMBOL MIN
VCC 3
VIH 2
VIL -0.3
II -2
VOH 2.4
VOL
IOZ -5
MAX UNITS NOTES
3.6 V
VCC + 0.3 V
35
0.8 V 35
2 µA 36
–V
0.4 V
5 µA
7

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관련 데이터시트

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4 MEG x 16 EDO DRAM

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