PDF PZTA92 Data sheet ( Hoja de datos )

Número de pieza	PZTA92
Descripción	PNP High Voltage Amplifier
Fabricantes	Fairchild Semiconductor
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No Preview Available ! March 2014 MMBTA92 / PZTA92 PNP High-Voltage Amplifier Description This device is designed for high-voltage driver applica- tions. Sourced from process 76. C E SOT-23 Mark: 2D B Figure 1. MMBTA92 Device Package C SOT-223 E C B Figure 2. PZTA92 Device Package Ordering Information Part Number MMBTA92 PZTA92 Top Mark 2D A92 Package SOT-23 3L SOT-223 4L Packing Method Tape and Reel Tape and Reel Absolute Maximum Ratings(1),(2) Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera- ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi- tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Values are at TA = 25°C unless otherwise noted. Symbol VCEO VCBO VEBO IC TJ, TSTG Parameter Collector-Emitter Voltage Collector-Base Voltage Emitter-Base Voltage Collector Current - Continuous Operating and Storage Junction Temperature Range Value -300 -300 -5 -500 -55 to +150 Unit V V V mA °C Notes: 1. These ratings are based on a maximum junction temperature of 150°C. 2. These are steady-state limits. Fairchild Semiconductor should be consulted on applications involving pulsed or low-duty-cycle operations. © 1997 Fairchild Semiconductor Corporation MMBTA92 / PZTA92 Rev. 1.1.0 1 www.fairchildsemi.com 1 page Physical Dimensions 2.92±0.20 3 SOT-23 0.95 1.40 1.30+-00..1250 2.20 (0.29) 1 0.95 1.90 1.20 MAX (0.93) C GAGE PLANE 0.23 0.08 0.20 MIN (0.55) 2 0.60 0.37 0.20 A B 1.00 1.90 LAND PATTERN RECOMMENDATION SEE DETAIL A 0.10 0.00 0.10 C 2.40±0.30 NOTES: UNLESS OTHERWISE SPECIFIED 0.25 SEATING PLANE A) REFERENCE JEDEC REGISTRATION TO-236, VARIATION AB, ISSUE H. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS ARE INCLUSIVE OF BURRS, MOLD FLASH AND TIE BAR EXTRUSIONS. D) DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994. E) DRAWING FILE NAME: MA03DREV10 SCALE: 2X Figure 11. 3-LEAD, SOT23, JEDEC TO-236, LOW PROFILE (ACTIVE) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/dwg/MA/MA03D.pdf. For current tape and reel specifications, visit Fairchild Semiconductor’s online packaging area: http://www.fairchildsemi.com/packing_dwg/PKG-MA03D.pdf. © 1997 Fairchild Semiconductor Corporation MMBTA92 / PZTA92 Rev. 1.1.0 5 www.fairchildsemi.com 5 Page

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