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PDF LMU8UJC35 Data sheet ( Hoja de datos )
| Número de pieza | LMU8UJC35 | |
| Descripción | 8 x 8-bit Parallel Multiplier | |
| Fabricantes | LOGIC Devices Incorporated | |
| Logotipo |  |
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DEVICES INCORPORATED
DEVICES INCORPORATED
LMU08/8U
8 x 8-biLt PMaraUlle0l M8u/l8tipUlier
8 x 8-bit Parallel Multiplier
FEATURES
DESCRIPTION
u 20 ns Worst-Case Multiply Time
u Low Power CMOS Technology
u LMU08 Replaces TRW TMC208K
u LMU8U Replaces TRW TMC28KU
u Two’s Complement (LMU08), or
Unsigned Operands (LMU8U)
u Three-State Outputs
u Package Styles Available:
• 40-pin PDIP
• 44-pin PLCC, J-Lead
The LMU08 and LMU8U are high-
speed, low power 8-bit parallel
multipliers. They are pin-for-pin
equivalents with TRW TMC208K and
TMC28KU type multipliers. Full
military ambient temperature range
operation is attained by the use of
advanced CMOS technology.
Both the LMU08 and the LMU8U
produce the 16-bit product of two
8-bit numbers. The LMU08 accepts
operands in two’s complement format,
and produces a two’s complement
result. The product is provided in two
halves with the sign bit replicated as
the most significant bit of both halves.
LMU08/8U BLOCK DIAGRAM
CLK A
CLK B
A7-0
8
A REGISTER
B7-0
8
B REGISTER
This facilitates use of the LMU08
product as a double precision operand
in 8-bit systems. The LMU8U oper-
ates on unsigned data, producing an
unsigned magnitude result.
Both the LMU08 and the LMU8U
feature independently controlled
registers for both inputs and the
product, which along with three-state
outputs allows easy interfacing with
microprocessor busses. Provision is
made in the LMU08 and LMU8U for
proper rounding of the product to
8-bit precision. The round input is
loaded at the rising edge of the logical
OR of CLK A and CLK B for the
LMU08. The LMU8U latches RND on
the rising edge of CLK A only. In
either case, a ‘1’ is added in the most
significant position of the lower
product byte when RND is asserted.
Subsequent truncation of the least
significant product byte results in a
correctly rounded 8-bit result.
LMU08 Only
RND
CLK R
16
8
RESULT
8
REGISTER
OEM
8
R15-8
OEL
8
R7-0
1
Multipliers
08/16/2000–LDS.08/8U-R
1 page  
DEVICES INCORPORATED
LMU08/8U
8 x 8-bit Parallel Multiplier
NOTES
1. Maximum Ratings indicate stress
specifications only. Functional oper-
ation of these products at values beyond
those indicated in the Operating Condi-
tions table is not implied. Exposure to
maximum rating conditions for ex-
tended periods may affect reliability.
2. The products described by this spec-
ification include internal circuitry de-
signed to protect the chip from damag-
ing substrate injection currents and ac-
cumulations of static charge. Neverthe-
less, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to
avoid exposure to excessive electrical
stress values.
3. Thisdeviceprovideshardclampingof
transient undershoot and overshoot. In-
put levels below ground or above VCC
will be clamped beginning at –0.6 V and
VCC + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of –0.5 V to +7.0 V. Device opera-
tion will not be adversely affected, how-
ever, input current levels will be well in
excess of 100 mA.
4. Actual test conditions may vary from
those designated but operation is guar-
anteed as specified.
5. Supply current for a given applica-
tion can be accurately approximated by:
where
NCV2 F
4
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing ev-
ery cycle and no load, at a 5 MHz clock
rate.
7. Tested with all inputs within 0.1 V of
VCC or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tDIS test), and input levels of nominally
0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified IOH and IOL at an output
voltage of VOH min and VOL max
respectively. Alternatively, a diode
bridge with upper and lower current
sources of IOH and IOL respectively,
and a balancing voltage of 1.5 V may be
used. Parasitic capacitance is 30 pF
minimum, and may be distributed.
This device has high-speed outputs ca-
pable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:
a. A 0.1 µF ceramic capacitor should be
installed between VCC and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
should be installed between device VCC
and the tester common, and device
ground and tester common.
b. Ground and VCC supply planes
must be brought directly to the DUT
socket or contactor fingers.
c. Input voltages should be adjusted to
compensate for inductive ground and VCC
noise to maintain required DUT input
levels relative to the DUT ground pin.
10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter-
nal system must supply at least that
much time to meet the worst-case re-
quirements of all parts. Responses from
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. For the tENA test, the transition is
measured to the 1.5 V crossing point
with datasheet loads. For the tDIS test,
the transition is measured to the
±200mV level from the measured
steady-state output voltage with
±10mA loads. The balancing volt-
age, VTH, is set at 3.5 V for Z-to-0
and 0-to-Z tests, and set at 0 V for Z-
to-1 and 1-to-Z tests.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
FIGURE A. OUTPUT LOADING CIRCUIT
S1
DUT
CL
IOL
VTH
IOH
FIGURE B. THRESHOLD LEVELS
tENA
tDIS
OE 1.5 V
1.5 V
Z0
1.5 V
VOL* 0.2 V
3.5V Vth
0Z
Z1
1.5 V
VOH* 0.2 V
1Z
0V Vth
VOL* Measured VOL with IOH = –10mA and IOL = 10mA
VOH* Measured VOH with IOH = –10mA and IOL = 10mA
Multipliers
5 08/16/2000–LDS.08/8U-R
5 Page | ||
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| PDF Descargar | [ Datasheet LMU8UJC35.PDF ] | |
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