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PDF PHN210 Data sheet ( Hoja de datos )
| Número de pieza | PHN210 | |
| Descripción | Dual N-channel enhancement mode TrenchMOS transistor | |
| Fabricantes | NXP Semiconductors | |
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Philips Semiconductors
Dual N-channel enhancement mode
TrenchMOSTM transistor
Product specification
PHN210
FEATURES
• Dual device
• Low threshold voltage
• Fast switching
• Logic level compatible
• Surface mount package
SYMBOL
d1 d1 d2 d2
s1 g1 s2 g2
QUICK REFERENCE DATA
VDS = 30 V
ID = 3.4 A
RDS(ON) ≤ 100 mΩ (VGS = 10 V)
RDS(ON) ≤ 200 mΩ (VGS = 4.5 V)
GENERAL DESCRIPTION
Dual N-channel enhancement
mode field-effect transistor in a
plastic envelope using ’trench’
technology.
Applications:-
• Motor and relay drivers
• d.c. to d.c. converters
• Logic level translator
The PHN210 is supplied in the
SOT96-1 (SO8) surface mounting
package.
PINNING
PIN
DESCRIPTION
1 source 1
2 gate 1
3 source 2
4 gate 2
5,6 drain 2
7,8 drain 1
SOT96-1
876 5
pin 1 index
1 23
4
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDS
VDS
VDGR
VGS
ID
ID
IDM
Ptot
Tstg, Tj
Repetitive peak drain-source
voltage
Continuous drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current per MOSFET1
Drain current per MOSFET (both
MOSFETs conducting)1
Drain current per MOSFET (pulse
peak value)
Total power dissipation (either or
both MOSFETs conducting)1
Storage & operating temperature
Tj = 25 ˚C to 150˚C
RGS = 20 kΩ
Ta = 25 ˚C
Ta = 70 ˚C
Ta = 25 ˚C
Ta = 70 ˚C
Ta = 25 ˚C
Ta = 25 ˚C
Ta = 70 ˚C
MIN.
-
-
-
-
-
-
-
-
-
-
-
- 65
MAX.
30
30
30
± 20
3.4
2.8
2.4
1.9
14
2
1.3
150
UNIT
V
V
V
V
A
A
A
A
A
W
W
˚C
1 Surface mounted on FR4 board, t ≤ 10 sec
February 1999
1
Rev 1.000
1 page  
Philips Semiconductors
Dual N-channel enhancement mode
TrenchMOSTM transistor
Product specification
PHN210
1E-01
Sub-Threshold Conduction
1E-02
1E-03
min typ max
1E-04
1E-05
1E-06
01234
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
5
Capacitances, Ciss, Coss, Crss (pF)
1000
100
Ciss
Coss
Crss
10
0.1
1 10
Drain-Source Voltage, VDS (V)
100
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
Source-Drain Diode Current, IF (A)
10
9 VGS = 0 V
8
7
6 150 C
5
4 Tj = 25 C
3
2
1
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5
Drain-Source Voltage, VSDS (V)
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
Non-repetitive Avalanche current, IAS (A)
10
PHN210
25 C
1
VDS
Tj prior to avalanche =125 C
tp
ID
0.1
1E-06
1E-05
1E-04
1E-03
Avalanche time, tp (s)
1E-02
Fig.15. Maximum permissible non-repetitive
avalanche current (IAS) versus avalanche time (tp);
unclamped inductive load
Gate-source voltage, VGS (V)
15
14 ID = 2.3A
13
12
Tj = 25 C
11 VDD = 15 V
10
9
8
7
6
5
4
3
2
1
0
0 1 2 3 4 5 6 7 8 9 10
Gate charge, QG (nC)
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); parameter VDS
February 1999
5
Rev 1.000
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet PHN210.PDF ] | |
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