74VHC00 데이터시트 PDF

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74VHC00

QUAD 2-INPUT NAND GATE

s HIGH SPEED: tPD = 3.7ns (TYP.) at VCC = 5V

s LOW POWER DISSIPATION:

ICC = 2 µA (MAX.) at TA=25°C

s HIGH NOISE IMMUNITY:

VNIH = VNIL = 28% VCC (MIN.)

s POWER DOWN PROTECTION ON INPUTS

s SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 8mA (MIN)

s BALANCED PROPAGATION DELAYS:

tPLH ≅ tPHL

s OPERATING VOLTAGE RANGE:

VCC(OPR) = 2V to 5.5V

s PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 00

s IMPROVED LATCH-UP IMMUNITY

s LOW NOISE: VOLP = 0.8V (MAX.)

DESCRIPTION

The 74VHC00 is an advanced high-speed CMOS

QUAD 2-INPUT NAND GATE fabricated with

sub-micron silicon gate and double-layer metal

wiring C2MOS technology.

The internal circuit is composed of 3 stages

including buffer output, which provides high noise

immunity and stable output.

SOP

TSSOP

Table 1: Order Codes

PACKAGE

SOP

TSSOP

T&R

74VHC00MTR

74VHC00TTR

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage. This device can be

used to interface 5V to 3V.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

Figure 1: Pin Connection And IEC Logic Symbols

November 2004

Rev. 5

1/11

74VHC00

Table 8: Capacitive Characteristics

Test Condition

Value

Symbol

Parameter

CIN Input Capacitance

CPD Power Dissipation

Capacitance

(note 1)

TA = 25°C

-40 to 85°C -55 to 125°C Unit

Min. Typ. Max. Min. Max. Min. Max.

6 10 10 10 pF

19 pF

1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without

load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/4 (per gate)

Table 9: Dynamic Switching Characteristics

Test Condition

Value

Symbol

Parameter

VOLP

VOLV

VIHD

VILD

Dynamic Low

Voltage Quiet

Output (note 1, 2)

Dynamic High

Voltage Input

(note 1, 3)

Dynamic Low

Voltage Input

(note 1, 3)

VCC

(V)

5.0

5.0

5.0

CL = 50 pF

TA = 25°C

-40 to 85°C -55 to 125°C Unit

Min. Typ. Max. Min. Max. Min. Max.

0.3 0.8

-0.8 -0.3

V

3.5 V

1.5 V

1) Worst case package.

2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n-1) outputs switching and one output at GND.

3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (VILD), 0V to threshold

(VIHD), f=1MHz.

Figure 3: Test Circuit

CL =15/50pF or equivalent (includes jig and probe capacitance)

RT = ZOUT of pulse generator (typically 50Ω)

4/11

DIM.

A

A1

A2

b

c

D

E

E1

e

K

L

74VHC00

MIN.

0.05

0.8

0.19

0.09

4.9

6.2

4.3

0˚

0.45

TSSOP14 MECHANICAL DATA

mm.

TYP

1

5

6.4

4.4

0.65 BSC

0.60

MAX.

1.2

0.15

1.05

0.30

0.20

5.1

6.6

4.48

8˚

0.75

MIN.

inch

TYP.

0.002

0.031

0.007

0.004

0.193

0.244

0.169

0˚

0.018

0.004

0.039

0.197

0.252

0.173

0.0256 BSC

0.024

MAX.

0.047

0.006

0.041

0.012

0.0089

0.201

0.260

0.176

8˚

0.030

A A2

A1 b

e

D

c

KL

E

PIN 1 IDENTIFICATION

1

E1

0080337D

7/11

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