74VHCT00 데이터시트 PDF

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® 74VHCT00A

QUAD 2-INPUT NAND GATE

s HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 5V

s LOW POWER DISSIPATION:

ICC = 2 µA (MAX.) at TA = 25 oC

s COMPATIBLE WITH TTL OUTPUTS:

VIH = 2V (MIN), VIL = 0.8V (MAX)

s POWER DOWN PROTECTION ON INPUTS &

OUTPUTS

s SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 8 mA (MIN)

s BALANCED PROPAGATION DELAYS:

tPLH ≅ tPHL

s OPERATING VOLTAGE RANGE:

VCC (OPR) = 4.5V to 5.5V

s PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 00

s IMPROVED LATCH-UP IMMUNITY

s LOW NOISE: VOLP = 0.8V (Max.)

DESCRIPTION

The 74VHCT00A is an advanced high-speed

CMOS QUAD 2-INPUT NAND GATE fabricated

with sub-micron silicon gate and double-layer

metal wiring C2MOS technology.

PRELIMINARY DATA

M

(Micro Package)

T

(TSSOP Package)

ORDER CODES :

74VHCT00AM

74VHCT00AT

The internal circuit is composed of 3 stages

including buffer output, which provide high noise

immunity and stable output.

Power down protection is provided on all inputs

and outputs and 0 to 7V can be accepted on

inputs with no regard to the supply voltage. This

device can be used to interface 5V to 3V.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

August 1999

1/7

74VHCT00A

DYNAMIC SWITCHING CHARACTERISTICS

Symb ol

Parameter

Test Conditions

V CC

( V)

Value

TA = 25 oC

Min. Typ. Max.

-40 to 85 oC

Min . Max.

Un it

VOLP

VOLV

VIHD

Dynamic Low Voltage

Quiet Output (note 1, 2)

Dynamic High Voltage

Input (note 1, 3)

5.0

5.0

CL = 50 pF

0.4 0.8

-0.8 -0.4

2.0

V

VILD Dynamic Low Voltage

Input (note 1, 3)

5.0

0.8

1) Worst case package.

2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.0, (n -1) outputs switching and one output atGND.

3) Max number of data inputs (n) switching. (n-1) switching 0V to3.0V. Inputs under test switching: 3.0V to threshold (VILD), 0V to threshold (VIHD), f=1MHz.

TEST CIRCUIT

CL = 15/50 pF or equivalent (includes jig and probe capacitance)

RT = ZOUT of pulse generator (typically 50Ω)

WAVEFORM: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)

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74VHCT00A

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is

granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are

subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products

are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a trademark of STMicroelectronics

© 1999 STMicroelectronics – Printed in Italy – All Rights Reserved

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