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8XC562 데이터시트 PDF




NXP Semiconductors에서 제조한 전자 부품 8XC562은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 8XC562 기능
기능 80C51 FAMILY DERIVATIVES
제조업체 NXP Semiconductors
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8XC562 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.



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8XC562 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
80C51 FAMILY DERIVATIVES
8XC552/562 overview
1996 Aug 06
Philips
Semiconductors




8XC562 pdf, 반도체, 판매, 대치품
Philips Semiconductors
80C51 Family Derivatives
8XC552/562 overview
Table 1. 8XC552 Special Function Registers
SYMBOL DESCRIPTION
ACC*
Accumulator
DIRECT
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
ADDRESS MSB
LSB
E0H
E7 E6
E5
E4
E3
E2
E1
E0
RESET
VALUE
00H
ADCH# A/D converter high
C6H
xxxxxxxxB
ADCON# Adc control
C5H ADC.1 ADC.0 ADEX ADCI ADCS AADR2 AADR1 AADR0 xx000000B
B* B register
F0H
F7 F6
F5
F4
F3
F2
F1
F0 00H
CTCON# Capture control
EBH
CTN3 CTP3 CTN2 CTP2 CTN1 CTP1 CTN0 CTP0 00H
CTH3#
CTH2#
CTH1#
CTH0#
CMH2#
CMH1#
CMH0#
CTL3#
CTL2#
CTL1#
CTL0#
CML2#
CML1#
CML0#
Capture high 3
Capture high 2
Capture high 1
Capture high 0
Compare high 2
Compare high 1
Compare high 0
Capture low 3
Capture low 2
Capture low 1
Capture low 0
Compare low 2
Compare low 1
Compare low 0
CFH
CEH
CDH
CCH
CBH
CAH
C9H
AFH
AEH
ADH
ACH
ABH
AAH
A9H
xxxxxxxxB
xxxxxxxxB
xxxxxxxxB
xxxxxxxxB
00H
00H
00H
xxxxxxxxB
xxxxxxxxB
xxxxxxxxB
xxxxxxxxB
00H
00H
00H
DPTR:
DPH
DPL
Data pointer
(2 bytes)
Data pointer high
Data pointer low
83H
82H
00H
00H
AF AE
AD
AC
AB
AA
A9
A8
IEN0*# Interrupt enable 0
A8H EA EAD ES1 ES0 ET1 EX1 ET0 EX0 00H
EF EE
ED
EC
EB
EA
E9
E8
IEN1*# Interrupt enable 1
E8H ET2 ECM2 ECM1 ECM0 ECT3 ECT2 ECT1 ECT0 00H
BF BE
BD
BC
BB
BA
B9
B8
IP0*#
Interrupt priority 0
B8H – PAD PS1 PS0 PT1 PX1 PT0 PX0 x0000000B
FF FE
FD
FC
FB
FA
F9
F8
IP1*#
Interrupt priority 1
F8H PT2 PCM2 PCM1 PCM0 PCT3 PCT2 PCT1 PCT0 00H
P5# Port 5
C4H
ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 xxxxxxxxB
C7 C6
C5
C4
C3
C2
C1
C0
P4# Port 4
C0H
CMT1 CMT0 CMSR5 CMSR4 CMSR3 CMSR2 CMSR1 CMSR0 FFH
B7 B6
B5
B4
B3
B2
B1
B0
P3* Port 3
B0H
RD WR
T1
T0
INT1
INT0
TXD
RXD FFH
A7 A6
A5
A4
A3
A2
A1
A0
P2* Port 2
A0H A15 A14 A13 A12 A11 A10 A9
A8 FFH
97 96
95
94
93
92
91
90
P1* Port 1
90H SDA SCL RT2 T2 CT3I CT2I CT1I CT0I FFH
87 86
85
84
83
82
81
80
P0* Port 0
80H AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 FFH
PCON# Power control
87H SMOD –
WLE GF1 GF0
PD
IDL 00xx0000B
D7 D6
D5
D4
D3
D2
D1
D0
PSW*
Program status word
D0H
CY AC F0 RS1 RS0 OV
* SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs.
F1
P 00H
1996 Aug 06
4

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8XC562 전자부품, 판매, 대치품
Philips Semiconductors
80C51 Family Derivatives
8XC552/562 overview
CT0I
INT
CTI0
CT1I
INT
CTI1
CT2I
INT
CTI2
CT3I
INT
CTI3
CT0 CT1 CT2 CT3
off
fosc 1/12
T2
RT2
T2ER
External reset
enable
S
S
S
S
S
S
TG
TG
STE
R
R
R
R
R
R
T
T
RTE
Prescaler
T2 Counter
8-bit overflow interrupt
16-bit overflow interrupt
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
I/O port 4
COMP INT COMP INT COMP INT
CMO (S)
CM1 (R)
CM2 (T)
S=
R=
T=
TG =
set
reset
toggle
toggle status
T2 SFR address:
TML2 = lower 8 bits
TMH2 = higher 8 bits
Figure 4. Block Diagram of Timer 2
SU00757
Measuring Time Intervals Using Capture Registers: When a
recurring external event is represented in the form of rising or falling
edges on one of the four capture pins, the time between two events
can be measured using Timer T2 and a capture register. When an
event occurs, the contents of Timer T2 are copied into the relevant
capture register and an interrupt request is generated. The interrupt
service routine may then compute the interval time if it knows the
previous contents of Timer T2 when the last event occurred. With a
12MHz oscillator, Timer T2 can be programmed to overflow every
524ms. When event interval times are shorter than this, computing
the interval time is simple, and the interrupt service routine is short.
For longer interval times, the Timer T2 extension routine may be
used.
Compare Logic: Each time Timer T2 is incremented, the contents
of the three 16-bit compare registers CM0, CM1, and CM2 are
compared with the new counter value of Timer T2. When a match is
found, the corresponding interrupt flag in TM2IR is set at the end of
the following cycle. When a match with CM0 occurs, the controller
sets bits 0-5 of port 4 if the corresponding bits of the set enable
register STE are at logic 1.
When a match with CM1 occurs, the controller resets bits 0-5 of port
4 if the corresponding bits of the reset/toggle enable register RTE
are at logic 1 (see Figure 6 for RTE register function). If RTE is “0”,
then P4.n is not affected by a match between CM1 or CM2 and
Timer 2. When a match with CM2 occurs, the controller “toggles”
bits 6 and 7 of port 4 if the corresponding bits of the RTE are at
logic 1. The port latches of bits 6 and 7 are not toggled.
Two additional flip-flops store the last operation, and it is these
flip-flops that are toggled.
Thus, if the current operation is “set,” the next operation will be
“reset” even if the port latch is reset by software before the “reset”
operation occurs. The first “toggle” after a chip RESET will set the
port latch. The contents of these two flip-flops can be read at STE.6
and STE.7 (corresponding to P4.6 and P4.7, respectively). Bits
STE.6 and STE.7 are read only (see Figure 7 for STE register
function). A logic 1 indicates that the next toggle will set the port
latch; a logic 0 indicates that the next toggle will reset the port latch.
CM0, CM1, and CM2 are reset by the RST signal.
The modified port latch information appears at the port pin during
S5P1 of the cycle following the cycle in which a match occurred. If
the port is modified by software, the outputs change during S1P1 of
the following cycle. Each port 4 bit can be set or reset by software at
any time. A hardware modification resulting from a comparator
match takes precedence over a software modification in the same
cycle. When the comparator results require a “set” and a “reset” at
the same time, the port latch will be reset.
Timer T2 Interrupt Flag Register TM2IR: Eight of the nine Timer
T2 interrupt flags are located in special function register TM2IR (see
Figure 8). The ninth flag is TM2CON.4.
The CT0I and CT1I flags are set during S4 of the cycle in which the
contents of Timer T2 are captured. CT0I is scanned by the interrupt
logic during S2, and CT1I is scanned during S3. CT2I and CT3I are
set during S6 and are scanned during S4 and S5. The associated
1996 Aug 06
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부품번호상세설명 및 기능제조사
8XC562

80C51 FAMILY DERIVATIVES

NXP Semiconductors
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