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기능 ACPI CardBus Controller
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OZ6812B 데이터시트, 핀배열, 회로
OZ6812
ACPI CardBus Controller
FEATURES
The OZ6812 is a PCMCIA R2/CardBus controller, providing
the most advanced design flexibility for PC Cards that
interface with advanced notebook designs.
ACPI-PCI Bus Power Management Interface
Specification Rev 1.1 Compliant
Supports OnNow LAN wakeup, OnNow Ring Indicate,
PCI CLKRUN#, PME#, and CardBus CCLKRUN#
Compliant with PCI specification V2.2, 1998 PC Card
Standard 7.0
Yenta™ PCI to PCMCIA CardBus Bridge register
compatible
ExCA (Exchangeable Card Architecture) compatible
registers mappable in memory and I/O space
IntelTM 82365SL PCIC Register Compatible
Supports PCMCIA_ATA Specification
Supports 5V/3.3V PC Cards and 3.3V CardBus cards
Supports single PC Card or CardBus slot with hot
insertion and removal
Supports multiple FIFOs for PCI/CardBus data transfer
Supports Direct Memory Access for PC/PCI and
PCI/Way on PC Card socket
Programmable interrupt protocol: PCI, PCI+ISA,
PCI/Way, or PC/PCI interrupt signaling modes
Win’98 IRQ and PC-98/99 compliant
Parallel or Serial interface for socket power control
devices including Micrel and TI
Zoomed Video Support
Integrated PC 98/99 -Subsystem Vendor ID support,
with auto lock bit
LED Activity Pins
ORDERING INFORMATION
OZ6812T - 144pin LQFP
OZ6812B - 144pin Mini-BGA
GENERAL DESCRIPTION
The OZ6812 is an ACPI and PC98/99 logo certified, high
performance, single slot PC Card controller with a
synchronous 32-bit bus master/target PCI interface. This
PC Card to PCI bridge host controller is compliant with the
1998 PC Card Standard. This standard incorporates the
new 32-bit CardBus while retaining the 16-bit PC Card
specification as defined by PCMCIA release 2.1. CardBus
is intended to support “temporal” add-in functions on PC
Cards, such as Memory cards, Network interfaces,
FAX/Modems and other wireless communication cards, etc.
The high performance and capability of the CardBus
interface will enable the development of many new
functions and applications.
The OZ6812 CardBus controller is compliant with the latest
ACPI-PCI Bus Power Management Interface Specification.
It supports all four power states and the PME# function for
maximum power savings and ACPI compliance. The device
also provides a power-down mode to allow host software to
reduce power consumption further by stopping internal
clock distribution as well as the PC Card socket clock. In
addition, an advanced CMOS process is utilized to
minimize system power consumption.
The OZ6812 single PCMCIA socket supports 3.3V/5V 8/16-
bit PC Card R2 card or 32-bit CardBus R3 card. The R2
card support is compatible with the Intel 82365SL PCIC
controller, and the R3 card support is fully compliant with
the 1998 PC Card Standard CardBus specification. The
OZ6812 is a stand alone device, which means that it does
not require an additional buffer chip for the PC Card socket
interface. In addition, the OZ6812 supports dynamic PC
Card hot insertion and removal, with auto configuration
capabilities.
The OZ6812 is fully compliant with the 33Mhz PCI Bus
specification, V2.2. It supports a master device with
internal CardBus direct data transfer. The OZ6812
implements a FIFO data buffer architecture between the
PCI bus and CardBus socket interface to enhance data
transfers to CardBus devices. The bi-directional FIFO
buffer (composed of 16 double words) permits the OZ6812
to accept data from a target bus (PCI or CardBus interface)
while simultaneously transferring data. This architecture
not only speeds up data transfers but also prevents system
deadlocks.
04/25/00
Copyright 2000 by O2Micro
OZ6812-SF-1.5
All Rights Reserved
Page 1
Patent Pending




OZ6812B pdf, 반도체, 판매, 대치품
Pin List
Bold Text = Normal Default Pin Name
OZ6812
PCI Bus Interface Pins
Pin Name
AD[31:0]
C/BE[3:0]#
FRAME#
IRDY#
TRDY#
STOP#
IDSEL
DEVSEL#
PERR#
SERR#
Description
PCI Bus Address Input / Data: These pins
connect to PCI bus signals AD[31:0]. A Bus
transaction consists of an address phase followed
by one or more data phases.
PCI Bus Command / Byte Enable: The
command signaling and byte enables are
multiplexed on the same pins. During the address
phase of a transaction, C/BE[3:0]# are interpreted
as the bus commands. During the data phase,
C/BE[3:0]# are interpreted as byte enables. The
byte enables are to be valid for the entirety of
each data phase, and they indicate which bytes in
the 32-bit data path are to carry meaningful data
for the current data phase.
Cycle Frame: This input indicates to the OZ6812
that a bus transaction is beginning. While
FRAME# is asserted, data transfers continue.
When FRAME# is de-asserted, the transaction is
in its final phase.
Initiator Ready: This input indicates the initiating
agents ability to complete the current data phase
of the transaction. IRDY# is used in conjunction
with TRDY#.
Target Ready: This output indicates target
Agent's the OZ6812s ability to complete the
current data phase of the transaction. TRDY# is
used in conjunction with IRDY#.
Stop: This output indicates the current target is
requesting the master to stop the current
transaction.
Initialization Device Select: This input is used as
a chip select during configuration read and write
transactions. This is a point-to-point signal.
IDSEL can be used as a chip select during
configuration read and write transactions.
Device Select: This output is driven active LOW
when the PCI address is recognized as
supported, thereby acting as the target for the
current PCI cycle. The Target must respond
before timeout occurs or the cycle will terminate.
Parity Error: The output is driven active LOW
when a data parity error is detected during a write
phase.
System Error: This output is driven active LOW
to indicate an address parity error.
Pin Number
LQFP
BGA
3-5, 7-11, 15- D4, B1, C2-1,
17, 19, 23-26, D2, E4, D1, E3,
38-41, 43, 45- F3, F1, F2, G1,
47, 49, 51-57 H2-3, J1, H4,
M2, K4, N2,
M3, N3, K5,
N4, L5, N5, L6,
N6, M6, L7, N7,
M7, K7
12, 27, 37, 48 E2, J2, N1, M5
28 K1
29 J3
31 L1
33 K3
13 E1
32 J4
34 M1
35 L2
Input
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
-
-
Type
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
TO
TO
Power
Rail
PCI_Vcc
PCI_Vcc
PCI_Vcc
PCI_Vcc
PCI_Vcc
PCI_Vcc
PCI_Vcc
PCI_Vcc
PCI_Vcc
PCI_Vcc
Drive
PCI
Spec
PCI
Spec
PCI
Spec
PCI
Spec
PCI
Spec
PCI
Spec
PCI
Spec
PCI
Spec
PCI
Spec
PCI
Spec
OZ6812-SF-1.5
Page 4

4페이지










OZ6812B 전자부품, 판매, 대치품
PC Card Socket Interface Pins
OZ6812
Refer to PCI Bus Interface pin descriptions for details on CardBus function.
EXCEPTIONS: CCD[2:1]#, CAUDIO, CSTSCHG, CVS[2:1]
Pin Name
REG#/
CCBE3#
A[25:24]/
CAD[19, 17]
A23/
CFRAME#
A22/
CTRDY#
A21/
CDEVSEL#
A20/
CSTOP#
A19/
CBLOCK#
A18/
RFU
A17/
CAD16
A16/
CCLK#
Description
Register Access: During PC Card memory cycles,
this output chooses between Attribute and Common
Memory. During I/O cycles for non-DMA transfers,
this signal is active (low). During ATA mode, this
signal is always inactive. For DMA cycles on the
OZ6812 to a DMA-capable card, REG# becomes
DACK to the PCMCIA card.
CardBus Command Byte Enable: In CardBus
mode, this pin is the CCBE3#.
Address: PC Card socket address 25:24 outputs.
CardBus Address/Data: CardBus mode, these pins
are the CAD bits 19 and 17.
Address: PC Card socket address 23 output.
CardBus Frame: In CardBus mode, this pin is the
CFRAME# signal.
Address: PC Card socket address 22 output.
CardBus Target Ready: In CardBus mode, this pin
is the CTRDY# signal.
Address: PC Card socket address 21 output.
CardBus Device Select: In CardBus mode, this pin
is the CDEVSEL# signal.
Address: PC Card socket address 20 output.
CardBus Stop: In CardBus mode, this pin is the
CSTOP# signal.
Address: PC Card socket address 19 output.
CardBus Lock: In CardBus mode, this signal is the
CBLOCK# signal used for locked transactions.
Address: PC Card socket address 18 output.
Reserved: In CardBus mode, this pin is reserved for
future use.
Address: PC Card socket address 17 output.
CardBus Address/Data: In CardBus mode, this pin
is the CAD bit 16.
Address: PC Card socket address 16 output.
CardBus Clock: In CardBus mode, this pin supplies
the clock to the inserted card.
Pin Number
LQFP
BGA
125 B8
Input Type
TTL I/O
Power
Rail
Socket
_Vcc
Drive
CardBus
spec.
116, 113
111
109
107
105
103
100
98
108
B10, B11
D10
A13
C12
D11
C13
D13
F10
C11
TTL I/O
TTL I/O
TTL I/O-
PU
TTL I/O-
PU
TTL I/O-
PU
TTL I/O-
PU
TTL TO
TTL I/O
TTL I/O
Socket CardBus
_Vcc
spec.
Socket CardBus
_Vcc
spec.
Socket CardBus
_Vcc
spec.
Socket CardBus
_Vcc
spec.
Socket CardBus
_Vcc
spec.
Socket CardBus
_Vcc
spec.
Socket CardBus
_Vcc
spec.
Socket CardBus
_Vcc
spec.
Socket CardBus
_Vcc
spec.
OZ6812-SF-1.5
Page 7

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