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74HCT161 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 74HCT161
기능 Presettable synchronous 4-bit binary counter asynchronous reset
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74HCT161 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT161
Presettable synchronous 4-bit
binary counter; asynchronous reset
Product specification
File under Integrated Circuits, IC06
December 1990




74HCT161 pdf, 반도체, 판매, 대치품
Philips Semiconductors
Presettable synchronous 4-bit binary
counter; asynchronous reset
Product specification
74HC/HCT161
Fig.4 Functional diagram.
FUNCTION TABLE
OPERATING MODE
reset (clear)
parallel load
count
hold
(do nothing)
MR
L
H
H
H
H
H
CP
X
X
X
INPUTS
CEP
X
X
X
h
I
X
CET
X
X
X
h
X
I
PE
X
I
I
h
h
h
Dn
X
I
h
X
X
X
OUTPUTS
Qn
L
L
H
count
qn
qn
TC
L
L
(1)
(1)
(1)
L
Note
1. The TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH).
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the
LOW-to-HIGH CP transition
X = don’t care
= LOW-to-HIGH CP transition
December 1990
4

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74HCT161 전자부품, 판매, 대치품
Philips Semiconductors
Presettable synchronous 4-bit binary
counter; asynchronous reset
Product specification
74HC/HCT161
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
SYMBOL PARAMETER
74HC
UNIT
+25 40 to +85 40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Qn
61
22
18
tPHL/ tPLH propagation delay
CP to TC
69
25
20
tPHL propagation delay
MR to Qn
63
23
18
tPHL propagation delay
MR to TC
63
23
18
tPHL/ tPLH propagation delay
CET to TC
33
12
10
tTHL/ tTLH output transition time
19
7
6
tW
clock pulse width
80 22
HIGH or LOW
16 8
14 6
tW master reset pulse 80 19
width; LOW
16 7
14 6
trem removal time
MR to CP
100 19
20 7
17 6
tsu set-up time
Dn to CP
80 25
16 9
14 7
tsu set-up time
PE to CP
100 30
20 11
17 9
190 240
38 48
32 41
215 270
43 54
37 46
210 265
42 53
36 45
220 275
44 55
37 47
150 190
30 38
26 33
75 95
15 19
13 16
100
20
17
100
20
17
125
25
21
100
20
17
125
25
21
285
57
48
325
65
55
315
63
54
330
66
56
225
45
38
110
22
19
120
24
20
120
24
20
150
30
26
120
24
20
150
30
26
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TEST CONDITIONS
VCC
(V)
WAVEFORMS
2.0 Fig.8
4.5
6.0
2.0 Fig.8
4.5
6.0
2.0 Fig.9
4.5
6.0
2.0 Fig.9
4.5
6.0
2.0 Fig.10
4.5
6.0
2.0 Figs 8 and 10
4.5
6.0
2.0 Fig.8
4.5
6.0
2.0 Fig.9
4.5
6.0
2.0 Fig.9
4.5
6.0
2.0 Fig.11
4.5
6.0
2.0 Fig.11
4.5
6.0
December 1990
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