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PDF MT5C1008 Data sheet ( Hoja de datos )
| Número de pieza | MT5C1008 | |
| Descripción | 128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS | |
| Fabricantes | ASI | |
| Logotipo |  |
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Austin Semiconductor, Inc.
SRAM
MT5C1008
128K x 8 SRAM
WITH DUAL CHIP ENABLE
AVAILABLE AS MILITARY
SPECIFICATIONS
•SMD 5962-89598
•MIL-STD-883
FEATURES
• High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns
• Battery Backup: 2V data retention
• Low power standby
• High-performance, low-power CMOS process
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE1\, CE2, and OE\
options.
• All inputs and outputs are TTL compatible
OPTIONS
• Timing
12ns access
15ns access
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
MARKING
-12 (contact factory)
-15
-20
-25
-35
-45
-55*
-70*
• Package(s)•
Ceramic DIP (400 mil)
Ceramic DIP (600 mil)
Ceramic LCC
Ceramic LCC
Ceramic Flatpack
Ceramic SOJ
Ceramic SOJ
C No. 111
CW No. 112
EC No. 207
ECA No. 208
F No. 303
DCJ No. 501
SOJ No. 507
• 2V data retention/low power L
*Electrical characteristics identical to those provided for the 45ns
access devices.
For more products and information
please visit our web site at
www.austinsemiconductor.com
PIN ASSIGNMENT
(Top View)
32-Pin DIP (C, CW)
32-Pin CSOJ (SOJ)
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 A15
30 CE2
29 WE\
28 A13
27 A8
26 A9
25 A11
24 OE\
23 A10
22 CE\
21 DQ8
20 DQ7
19 DQ6
18 DQ5
17 DQ4
32-Pin Flat Pack (F)
32-Pin LCC (EC)
32-Pin SOJ (DCJ)
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 A15
30 CE2
29 WE\
28 A13
27 A8
26 A9
25 A11
24 OE\
23 A10
22 CE\
21 DQ8
20 DQ7
19 DQ6
18 DQ5
17 DQ4
32-Pin LCC (ECA)
NC 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
DQ1 13
DQ2 14
DQ3 15
VSS 16
32 VCC
31 A15
30 CE2
29 WE\
28 A13
27 A8
26 A9
25 A11
24 OE\
23 A10
22 CE\
21 DQ8
20 DQ7
19 DQ6
18 DQ5
17 DQ4
4 3 2 1 32 31 30
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
5
6
7
8
9
10
11
12
13
29 WE\
28 A13
27 A8
26 A9
25 A11
24 OE \
23 A10
22 CE1\
21 DQ8
14 15 16 17 18 19 20
GENERAL DESCRIPTION
The MT5C1008 SRAM employs high-speed, low power
CMOS designs using a four-transistor memory cell, and are
fabricated using double-layer metal, double-layer polysilicon
technology.
For design flexibility in high-speed memory
applications, this device offers dual chip enables (CE1\, CE2)
and output enable (OE\). These control pins can place the
outputs in High-Z for additional flexibility in system design.
All devices operate from a single +5V power supply and all
inputs and outputs are fully TTL compatible.
Writing to these devices is accomplished when write
enable (WE\) and CE1\ inputs are both LOW and CE2 is HIGH.
Reading is accomplished when WE\ and CE2 remain HIGH and
CE1\ and OE\ go LOW. The devices offer a reduced power
standby mode when disabled, allowing system designs to
achieve low standby power requirements.
The “L” version offers a 2V data retention mode, re-
ducing current consumption to 1mA maximum.
MT5C1008
Rev. 6.5 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
1 page  
Austin Semiconductor, Inc.
SRAM
MT5C1008
ACTEST CONDITIONS
Input pulse levels ................................... Vss to 3.0V
Input rise and fall times ....................................... 5ns
Input timing reference levels ............................. 1.5V
Output reference levels ..................................... 1.5V
Output load .............................. See Figures 1 and 2
Q
255
+5V
480
Q
30
255
+5V
480
5 pF
Fig. 1 Output Load
Equivalent
Fig. 2 Output Load
Equivalent
NOTES
1. All voltages referenced to VSS (GND).
2. -2V for pulse width < 20ns
3. ICC is dependent on output loading and cycle rates.
The specified value applies with the outputs
unloaded, and f = 1 Hz.
tRC (MIN)
4. This parameter is guaranteed but not tested.
5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6. tLZCE, tLZWE, tLZOE, tHZCE, tHZOE and tHZWE
are specified with CL = 5pF as in Fig. 2. Transition is
measured ±200mV typical from steady state voltage,
allowing for actual tester RC time constant.
7. At any given temperature and voltage condition,
tHZCE is less than tLZCE, and tHZWE is less than
tLZWE and tHZOE is less than tLZOE.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11. tRC = Read Cycle Time.
12. CE2 timing is the same as CE1\ timing. The
waveform is inverted.
13. Chip enable (CE1\, CE2) and write enable (WE\) can
initiate and terminate a WRITE cycle.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
VCC for Retention Data
CONDITIONS
SYMBOL
VDR
MIN
2
MAX
---
Data Retention Current
CE\ > (VCC - 0.2V)
VIN > (VCC - 0.2V)
or < 0.2V, f=0
VCC = 2V
ICCDR
1.0
Chip Deselect to Data
Retention Time
Operation Recovery Time
tCDR 0 ---
tR tRC
UNITS NOTES
V
mA
ns 4
ns 4, 11
LOW Vcc DATA RETENTION WAVEFORM
MT5C1008
Rev. 6.5 7/02
VCC
CE1\
CE2
tCDR
VIH
VIL
111122223333444455556666777788889999
VIH
VIL
111122223333444455556666777788889999
DATA RETENTION MODE
4.5V
VDR > 2V
4.5V
tR
VDR
<VSS + 0.2V
111122223333444455556666111177772111122288883222233343343344
111122223333444455556666111177772111122288883222233343343344
111122223333DON’T CARE
1111222233334444UNDEFINED
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
5 Page 
Austin Semiconductor, Inc.
MECHANICAL DEFINITIONS*
ASI Case #208 (Package Designator ECA)
SMD 5962-89598, Case Outline M
D1
L1
E E1
e
See Detail A
SRAM
MT5C1008
A
D
Detail A
L
b
b1
SYMBOL
A
b
b1
b2
D
D1
E
E1
e
L
L1
SMD SPECIFICATIONS
MIN MAX
0.060
0.120
0.022
0.028
0.004
0.014
0.040
---
0.442
0.458
0.300 BSC
0.540
0.560
0.400 BSC
0.050 BSC
0.045
0.055
0.075
0.095
b2
*All measurements are in inches.
MT5C1008
Rev. 6.5 7/02
11
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet MT5C1008.PDF ] | |
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