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PDF AT40Kxx Data sheet ( Hoja de datos )
| Número de pieza | AT40Kxx | |
| Descripción | 5K - 50K Gates Coprocessor FPGA with FreeRAM | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Ultra High Performance
– System Speeds to 100 MHz
– Array Multipliers > 50 MHz
– 10 ns Flexible SRAM
– Internal Tri-state Capability in Each Cell
• FreeRAM™
– Flexible, Single/Dual Port, Synchronous/Asynchronous 10 ns SRAM
– 2,048 - 18,432 Bits of Distributed SRAM Independent of Logic Cells
• 128 - 384 PCI Compliant I/Os
– 3V/5V Capability
– Programmable Output Drive
– Fast, Flexible Array Access Facilitates Pin Locking
– Pin-compatible with XC4000, XC5200 FPGAs
• 8 Global Clocks
– Fast, Low Skew Clock Distribution
– Programmable Rising/Falling Edge Transitions
– Distributed Clock Shutdown Capability for Low Power Management
– Global Reset/Asynchronous Reset Options
– 4 Additional Dedicated PCI Clocks
• Cache Logic® Dynamic Full/Partial Re-configurability In-System
– Unlimited Re-programmability via Serial or Parallel Modes
– Enables Adaptive Designs
– Enables Fast Vector Multiplier Updates
– QuickChange™ Tools for Fast, Easy Design Changes
• Pin-compatible Package Options
– Plastic Leaded Chip Carriers (PLCC)
– Thin, Plastic Quad Flat Packs (LQFP, TQFP, PQFP)
– Ball Grid Arrays (BGAs)
• Industry-standard Design Tools
– Seamless Integration (Libraries, Interface, Full Back-annotation) with
Concept®, Everest, Exemplar™, Mentor®, OrCAD®, Synario™, Synopsys®,
Verilog®, Veribest®, Viewlogic®, Synplicity®
– Timing Driven Placement & Routing
– Automatic/Interactive Multi-chip Partitioning
– Fast, Efficient Synthesis
– Over 75 Automatic Component Generators Create 1000s
of Reusable, Fully Deterministic Logic and RAM Functions
• Intellectual Property Cores
– Fir Filters, UARTs, PCI, FFT and Other System Level Functions
• Easy Migration to Atmel Gate Arrays for High Volume Production
• Supply Voltage 5V for AT40K, and 3.3V for AT40KLV
5K - 50K Gates
Coprocessor
FPGA with
FreeRAM™
AT40K05
AT40K05LV
AT40K10
AT40K10LV
AT40K20
AT40K20LV
AT40K40
AT40K40LV
Rev. 0896C–FPGA–04/02
1
1 page  
AT40K/AT40KLV Series FPGA
Figure 2. Floor Plan (Representative Portion)(1)
RV = Vertical Repeater
RH = Horizontal Repeater
= Core Cell
RAM RV RV RV RV RAM RV RV RV RV RAM RV RV RV RV RAM
RH RH RH RH
RH RH RH RH
RH RH RH RH
RH RH RH RH
RAM RV RV RV RV RAM RV RV RV RV RAM RV RV RV RV RAM
RH RH RH RH
RH RH RH RH
RH RH RH RH
RH RH RH RH
RAM RV RV RV RV RAM RV RV RV RV RAM RV RV RV RV RAM
RH RH RH RH
RH RH RH RH
RH RH RH RH
RH RH RH RH
RAM RV RV RV RV RAM RV RV RV RV RAM RV RV RV RV RAM
Note:
1. Repeaters regenerate signals and can connect any bus to any other bus (all path-
ways are legal) on the same plane. Each repeater has connections to two adjacent
local-bus segments and two express-bus segments. This is done automatically using
the integrated development system (IDS) tool.
0896C–FPGA–04/02
5
5 Page 
RAM
AT40K/AT40KLV Series FPGA
32 x 4 dual-ported RAM blocks are dispersed throughout the array, see Figure 7. A 4-bit
Input Data Bus connects to four horizontal local buses distributed over four sector rows
(plane 1). A 4-bit Output Data Bus connects to four horizontal local buses distributed
over four sectors in the same column. A 5-bit Output Address Bus connects to five verti-
cal express buses in the same column. Ain (input address) and Aout (output address)
alternate positions in horizontally aligned RAM blocks. For the left-most RAM blocks,
Aout is on the left and Ain is on the right. For the right-most RAM blocks, Ain is on the
left and Aout is tied off, thus it can only be configured as a single port. For single-ported
RAM, Ain is the READ/WRITE address port and Din is the (bi-directional) data port.
Right-most RAM blocks can be used only for single-ported memories. WEN and OEN
connect to the vertical express buses in the same column.
Figure 7. RAM Connections (One Ram Block)
CLK
CLK
CLK
CLK
Din Dout
Ain Aout
32 x 4 RAM
WEN
OEN CLK
0896C–FPGA–04/02
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AT40Kxx.PDF ] | |
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