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39VF6401 데이터시트 PDF




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기능 SST39VF6401
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39VF6401 데이터시트, 핀배열, 회로
16 Mbit / 32 Mbit / 64 Mbit (x16) Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
SST39VF160x / 320x / 640x2.7V 16Mb / 32Mb / 64Mb (x16) MPF+ memories
FEATURES:
Preliminary Specifications
• Organized as 1M x16: SST39VF1601/1602
2M x16: SST39VF3201/3202
4M x16: SST39VF6401/6402
• Single Voltage Read and Write Operations
– 2.7-3.6V
• Superior Reliability
– Endurance: 100,000 Cycles (Typical)
– Greater than 100 years Data Retention
• Low Power Consumption (typical values at 5 MHz)
– Active Current: 9 mA (typical)
– Standby Current: 3 µA (typical)
– Auto Low Power Mode: 3 µA (typical)
• Hardware Block-Protection/WP# Input Pin
– Top Block-Protection (top 32 KWord)
for SST39VF1602/3202/6402
– Bottom Block-Protection (bottom 32 KWord)
for SST39VF1601/3201/6401
• Sector-Erase Capability
– Uniform 2 KWord sectors
• Block-Erase Capability
– Uniform 32 KWord blocks
• Chip-Erase Capability
• Erase-Suspend/Erase-Resume Capabilities
• Hardware Reset Pin (RST#)
• Security-ID Feature
– SST: 128 bits; User: 128 bits
• Fast Read Access Time:
– 70 ns
– 90 ns
• Latched Address and Data
• Fast Erase and Word-Program:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 40 ms (typical)
– Word-Program Time: 7 µs (typical)
• Automatic Write Timing
– Internal VPP Generation
• End-of-Write Detection
– Toggle Bits
– Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Packages Available
– 48-lead TSOP (12mm x 20mm)
– 48-ball TFBGA (6mm x 8mm) for 16M and 32M
– 48-ball TFBGA (8mm x 10mm) for 64M
PRODUCT DESCRIPTION
The SST39VF160x/320x/640x devices are 1M x16, 2M
x16, and 4M x16 respectively, CMOS Multi-Purpose
Flash Plus (MPF+) manufactured with SST’s proprietary,
high performance CMOS SuperFlash technology. The
split-gate cell design and thick-oxide tunneling injector
attain better reliability and manufacturability compared
with alternate approaches. The SST39VF160x/320x/640x
write (Program or Erase) with a 2.7-3.6V power supply.
These devices conform to JEDEC standard pinouts for
x16 memories.
Featuring high performance Word-Program, the
omSST39VF160x/320x/640x devices provide a typical Word-
.cProgram time of 7 µsec. These devices use Toggle Bit or
Data# Polling to indicate the completion of Program opera-
t4ution. To protect against inadvertent write, they have on-chip
hardware and Software Data Protection schemes.
eDesigned, manufactured, and tested for a wide spectrum of
eapplications, these devices are offered with a guaranteed
shtypical endurance of 100,000 cycles. Data retention is rated
taat greater than 100 years.
w.da©2003 Silicon Storage Technology, Inc.
S71223-03-000
11/03
ww 1
The SST39VF160x/320x/640x devices are suited for appli-
cations that require convenient and economical updating of
program, configuration, or data memory. For all system
applications, they significantly improve performance and
reliability, while lowering power consumption. They inher-
ently use less energy during Erase and Program than alter-
native flash technologies. The total energy consumed is a
function of the applied voltage, current, and time of applica-
tion. Since for any given voltage range, the SuperFlash
technology uses less current to program and has a shorter
erase time, the total energy consumed during any Erase or
Program operation is less than alternative flash technolo-
gies. These devices also improve flexibility while lowering
the cost for program, data, and configuration storage appli-
cations.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose
Erase and Program times increase with accumulated
Erase/Program cycles.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.




39VF6401 pdf, 반도체, 판매, 대치품
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
Preliminary Specifications
Data Protection
The SST39VF160x/320x/640x provide both hardware and
software features to protect nonvolatile data from inadvertent
writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Hardware Block Protection
The SST39VF1602/3202/6402 support top hardware block
protection, which protects the top 32 KWord block of the
device. The SST39VF1601/3201/6401 support bottom
hardware block protection, which protects the bottom 32
KWord block of the device. The Boot Block address ranges
are described in Table 2. Program and Erase operations
are prevented on the 32 KWord when WP# is low. If WP# is
left floating, it is internally held high via a pull-up resistor,
and the Boot Block is unprotected, enabling Program and
Erase operations on that block.
TABLE 2: BOOT BLOCK ADDRESS RANGES
Product
Address Range
Bottom Boot Block
SST39VF1601/3201/6401
000000H-007FFFH
Top Boot Block
SST39VF1602
SST39VF3202
SST39VF6402
0F8000H-0FFFFFH
1F8000H-1FFFFFH
3F8000H-3FFFFFH
T2.0 1223
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the
device to read array data. When the RST# pin is held low
for at least TRP, any in-progress operation will terminate and
return to Read mode. When no internal Program/Erase
operation is in progress, a minimum period of TRHR is
required after RST# is driven high before a valid Read can
take place (see Figure 15).
The Erase or Program operation that has been interrupted
needs to be reinitiated after the device resumes normal
operation mode to ensure data integrity.
Software Data Protection (SDP)
The SST39VF160x/320x/640x provide the JEDEC
approved Software Data Protection scheme for all data
alteration operations, i.e., Program and Erase. Any Pro-
gram operation requires the inclusion of the three-byte
sequence. The three-byte load sequence is used to initiate
the Program operation, providing optimal protection from
inadvertent Write operations, e.g., during the system
power-up or power-down. Any Erase operation requires the
inclusion of six-byte sequence. These devices are shipped
with the Software Data Protection permanently enabled.
See Table 6 for the specific software command codes. Dur-
ing SDP command sequence, invalid commands will abort
the device to read mode within TRC. The contents of DQ15-
DQ8 can be VIL or VIH, but no other value, during any SDP
command sequence.
Common Flash Memory Interface (CFI)
The SST39VF160x/320x/640x also contain the CFI infor-
mation to describe the characteristics of the device. In
order to enter the CFI Query mode, the system must write
three-byte sequence, same as product ID entry command
with 98H (CFI Query command) to address 5555H in the
last byte sequence. Once the device enters the CFI Query
mode, the system can read CFI data at the addresses
given in Tables 7 through 10. The system must write the
CFI Exit command to return to Read mode from the CFI
Query mode.
©2003 Silicon Storage Technology, Inc.
4
S71223-03-000
11/03

4페이지










39VF6401 전자부품, 판매, 대치품
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
Preliminary Specifications
TOP VIEW (balls facing down)
SST39VF1601/1602
6
A13 A12 A14 A15 A16 NC DQ15 VSS
5
A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6
4
WE# RST# NC A19 DQ5 DQ12 VDD DQ4
3
NC WP# A18 NC DQ2 DQ10 DQ11 DQ3
2
A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1
1
A3 A4 A2 A1 A0 CE# OE# VSS
ABCDEFGH
TOP VIEW (balls facing down)
SST39VF3201/3202
6
A13 A12 A14 A15 A16 NC DQ15 VSS
5
A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6
4
WE# RST# NC A19 DQ5 DQ12 VDD DQ4
3
NC WP# A18 A20 DQ2 DQ10 DQ11 DQ3
2
A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1
1
A3 A4 A2 A1 A0 CE# OE# VSS
ABCDEFGH
TOP VIEW (balls facing down)
SST39VF6401/6402
6
A13 A12 A14 A15 A16 NC DQ15 VSS
5
A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6
4
WE# RST# A21 A19 DQ5 DQ12 VDD DQ4
3
NC WP# A18 A20 DQ2 DQ10 DQ11 DQ3
2
A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1
1
A3 A4 A2 A1 A0 CE# OE# VSS
ABCDEFGH
FIGURE 2: PIN ASSIGNMENTS FOR 48-BALL TFBGA
©2003 Silicon Storage Technology, Inc.
7
S71223-03-000
11/03

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