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PDF TXC04236 Data sheet ( Hoja de datos )
| Número de pieza | TXC04236 | |
| Descripción | OC-3 Ethemet Over SONET Mapper | |
| Fabricantes | Transwitch | |
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EtherMap-3 Plus Device
OC-3 Ethernet over SONET Mapper
with Rapid Restoration
TXC-04236
DATA SHEET
FEATURES
• Eight 10/100 Mbit/s Ethernet ports, each using a SMII
interface
• Single 1000 Mbit/s Ethernet port, using a parallel GMII
interface (lead shared with SMII interfaces)
• Ethernet Management interface for control and configuration
of externally connected PHYs
• Provides IEEE 802.3 Half Duplex mode on 10/100 Mbit/s
and Full Duplex mode on 10/100/1000 Mbit/s Ethernet ports
• Provides IEEE 802.3 Management Statistics (RMON)
• Ethernet frame encapsulation/decapsulation protocols:
• ITU-T G.7041, Generic Framing Procedure (GFP)
• ITU-T X.86/X.85, Link Access Procedure SDH (LAPS)
• ITU-T Q.922, Link Access Procedure Frame Mode (LAPF)
• RFC1662/3518, PPP Bridging Control Protocol (BCP)
• Performs mapping/demapping of encapsulated Ethernet
frames into/from low order (VT1.5 SPE/VT2 SPE/VC-11/VC-
12) and high order (STS-1 SPE/VC-3) virtually concatenated
payloads
• Performs mapping/demapping of encapsulated Ethernet
frames into/from a single contiguous concatenated (STS-3c-
SPE/VC-4) payload or a single Low/High order
(VT1.5/VT2/VC-11/VC-12/STS-1/VC-3) payload
• Dynamic bandwidth allocation using on-chip LCAS
processing (ITU-T G.7042) for low and high order virtual
concatenated payloads
• Glueless memory interface to external 64/128/256 Mbit
SDRAMs
• Low Order POH and Pointer processing for 84/63
VT1.5/VT2/TU-11/TU-12 and 3 TU-3
• High Order POH processing for STS-1 SPE/VC-3/STS-3c
SPE/VC-4
• Byte-wide 19 MHz parallel Add and Drop Telecom Bus
interfaces
• Per-port Ethernet side and SONET/SDH system side
loopback for system level diagnostics
• 16-bit wide microprocessor interface, selectable between
Motorola or Intel
• Boundary scan (IEEE 1149.1 standard)
• + 3.3V and +1.8V power supplies, 5V tolerant I/O leads
• 400-lead plastic ball grid array package
(PBGA, 27 mm x 27 mm)
• Device Driver
DESCRIPTION
The EtherMap-3 Plus is a highly integrated EoS device that provides for
mapping of 10/100/1000 Mbit/s Ethernet into SONET/SDH STS-3/STM-1
Transport payloads. The device supports connection for up to eight 10/100
Mbit/s Ethernet ports, using SMII interfaces, or a single 1000 Mbit/s
Ethernet port, using a GMII interface. Ethernet frames are encapsulated
using either GFP, LAPS, LAPF or PPP/BCP protocol. The encapsulated
Ethernet frames are then mapped into either virtually concatenated low or
high order payloads, such as VT1.5 SPE/VT2 SPE/VC-11/VC-12/STS-1
SPE/VC-3, or into contiguously concatenated payloads such as STS-3c
SPE/VC-4. Low and high order SONET/SDH POH generation and
processing/termination is performed. A byte-wide parallel interface
Telecom Bus format provides the SONET/SDH interface and may support
either Drop bus or Add bus timing modes.
In addition to support for full-rate Ethernet transfer, over-subscribed
Ethernet transfers are also supported using back pressure mechanisms
(half and full duplex flow control) in order to prevent frame loss. External
SDRAM is used for buffering Ethernet frames to support bandwidth
oversubscription and flow control operation as well as receive
SONET/SDH container alignment and differential delay compensation of
low and high order virtually concatenated payloads.
For both low and high order virtually concatenated payloads, optional on-
chip standards based LCAS processing is provided to allow hitless
dynamic bandwidth adjustments.
A powerful hardware and RTOS independent EtherMap device driver
provides full access to all the features of the device through APIs. It utilizes
matched get/set functions and can be easily ported.
APPLICATIONS
• SONET/SDH add/drop and terminal multiplexers
• Multi-service access platforms (MSAP)
• Compact Access or CPE platforms
• IP DSLAMS
• Wireless Backhaul Electronics (RNC/BSC)
TELECOM BUS SIDE
+1.8V
+3.3V •
HO/LO HO/LO
RING POH
Ports Ports
Controls
CLOCKS
(SONET/SDH Ref,
System, One Sec.)
ETHERNET LINE SIDE
EtherMap-3 Plus
10/100 Mbit/s SMII (Port 1)
DROP Bus
.comADD Bus
OC-3 Ethernet over
SONET Mapper
with Rapid Restoration
TXC-04236
• / 1000 Mbit/s GMII
•
•
•
10/100 Mbit/s SMII (Port 8)
eet4u Microprocessor SDRAM
h Interface Interface
sU.S. and/or foreign patents issued or pending
taCopyright © 2004 TranSwitch Corporation
EtherMap, PHAST, TEMx28, TranSwitch and TXC
aare registered trademarks of TranSwitch Corporation
Boundary
Scan
Ethernet
Management
Interface
Document Number:
PRELIMINARY TXC-04236-MB, Ed. 3
July 2004
.d TranSwitch Corporation • 3 Enterprise Drive • Shelton, Connecticut 06484 • USA
www Tel: 203-929-8810 • Fax: 203-926-9453 • www.transwitch.com
1 page  
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
EtherMap-3 Plus
TXC-04236
Section
TABLE OF CONTENTS (cont.)
Page
Tables 132 through 154 - Configuration, Status and Alarms of the Low Order POH Monitor ..................... 308
Tables 155 through 162 - Configuration, Status and Alarms of the Low Order
Tx Alarm Indication (RING) Port .................................................................................................................. 316
Table 163 - Configuration of the Low Order Rx Alarm Indication (RING) Port ............................................ 317
Tables 164 through 166 - Configuration and Status of the general Low Order Interrupt Controller ............ 318
Table 167 - Configuration of the High Order Rx Alarm Indication (RING) Port ........................................... 318
Tables 168 through 176 - Configuration, Status and Alarms of the High Order
Tx Alarm Indication (RING) Port .................................................................................................................. 318
Tables 177 through 209 - Configuration, Status and Alarms of the High Order POH Monitor .................... 320
Tables 210 through 222 - Configuration, Status and Alarms of the TU-3 PTR Tracker .............................. 332
Tables 223 and 224 - Configuration of TU-3 Cross Connect ...................................................................... 334
Tables 225 through 237 - Configuration, Status and Alarms of the TU-3 PTR Generator .......................... 335
Tables 238 through 242 - Configuration of High Order (VC-3 and VC-4) POH Generator .......................... 337
Tables 243 through 250 - Configuration, Status and Alarms of the TU-3 Retimer ...................................... 339
Tables 251 through 258 - Configuration, Status and Alarms of the AU-3/4 Retimer ................................... 341
Tables 259 through 261 - Configuration and Status of the General High Order Interrupt Controller .......... 342
Tables 262 through 280 - Configuration, Status and Alarms of the Rx Combus Interface .......................... 343
Tables 281 through 302 - Configuration, Status and Alarms of the Tx Combus Interface .......................... 347
Tables 303 through 305 - Configuration and Status of the General Combus Interface Interrupt Controller 350
Tables 306 through 308 - Configuration and Status of the General VTMAPPER Interrupt Controller ........ 351
Alarms, Performance and Fault Monitoring .......................................................................................................... 353
Terminology ..................................................................................................................................................... 353
System Alarm (Raw, Unlatched Alarm) ....................................................................................................... 353
Alarm Event ................................................................................................................................................. 353
Latched Alarm ............................................................................................................................................. 353
Secondary Alarm Inhibition .......................................................................................................................... 353
Interrupt Mask .............................................................................................................................................. 354
Performance and Fault Monitoring (PM and FM) ........................................................................................ 354
Performance Monitoring (PM) ..................................................................................................................... 354
Fault Monitoring (FM) .................................................................................................................................. 354
1-Second Clock ........................................................................................................................................... 354
Performance Counters ................................................................................................................................ 354
Unlatched Alarms ............................................................................................................................................. 355
Inhibition of Secondary Unlatched Alarm Generation .................................................................................. 355
Latched Alarms ................................................................................................................................................ 355
Latched Alarm Bits for Interrupt Generation (Lalarm_name/L1alarm_name) .................................................. 356
Latched Alarm Masking Bits (Malarm_name) .................................................................................................. 357
Secondary Latched Alarm Inhibition ................................................................................................................ 358
Latched Alarm Bits for PM/FM (L2ALARM_name), Performance Monitoring
(PM Bits; Palarm_name) and Fault Monitoring (FM Bits; Falarm_name) ........................................................ 359
Positive Edge Events ................................................................................................................................... 360
Negative Edge Events ................................................................................................................................. 361
Positive or Negative Edge Events ............................................................................................................... 362
Overall Alarm Generation and PM/FM Process Diagram ................................................................................ 363
Performance Counters ..................................................................................................................................... 364
Scheme A - Counters with Roll-Over/Saturation Option .............................................................................. 364
Scheme B - Performance Counters with 1-second Shadow Register Option ............................................. 364
Alarm Feature Combinations ........................................................................................................................... 365
System Alarm, Interrupt, and PM/FM Hierarchy .............................................................................................. 366
Alarm Interrupt Tree ......................................................................................................................................... 368
Register Tree ................................................................................................................................................... 376
Mapper/Demapper Performance Monitoring .................................................................................................... 378
Mapper/Demapper Interrupt Tree ................................................................................................................ 379
Mapper/Demapper PM/FM Tree per Block .................................................................................................. 383
Mapper/Demapper Consequent Actions per Block ..................................................................................... 390
Package Information ............................................................................................................................................. 394
Ordering Information ............................................................................................................................................. 395
Related Products .................................................................................................................................................. 395
Standards Documentation Sources ...................................................................................................................... 396
List of Data Sheet Changes .................................................................................................................................. 398
Please note that TranSwitch provides documentation for all of its products. Current editions of many documents are available
from the Products page of the TranSwitch Web site at www.transwitch.com. Customers who are using a TranSwitch Product,
or planning to do so, should register with the TranSwitch Marketing Department to receive relevant updated and
supplemental documentation as it is issued. They should also contact the Applications Engineering Department to ensure
that they are provided with the latest available information about the product, especially before undertaking development of
new designs incorporating the product.
- 5 of 402 -
PRELIMINARY TXC-04236-MB, Ed. 3
July 2004
5 Page 
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
EtherMap-3 Plus
TXC-04236
LIST OF TABLES (cont.)
Table
Page
153 LO POH Monitor - Performance Counters (RW) ........................................................................................ 315
154 LO POH Monitor - Performance Counter Shadow Registers (RO) ............................................................ 315
155 Tx LO Ring Port - General Configuration (RW) .......................................................................................... 316
156 Tx LO Ring Port - Event Latch (COW-1) .................................................................................................... 316
157 Tx LO Ring Port - Performance Counters (RW) ......................................................................................... 316
158 Tx LO Ring Port - Performance Counter Shadow Registers (RO) ............................................................. 316
159 Tx LO Ring Port - Defects .......................................................................................................................... 317
160 Tx LO Ring Port - Interrupt Mask (RW) ...................................................................................................... 317
161 Tx LO Ring Port - Event Interrupt (RO) ...................................................................................................... 317
162 Tx LO Ring Port - Defect Interrupt (RO) ..................................................................................................... 317
163 Rx LO Ring Port - Configuration (RW) ....................................................................................................... 317
164 LO Interrupt Controller - Interrupts (RO) .................................................................................................... 318
165 LO Interrupt Controller - Interrupt Masks (RW) .......................................................................................... 318
166 LO Interrupt Controller - Summary (RO) .................................................................................................... 318
167 Rx HO Ring Port - Configuration (RW) ...................................................................................................... 318
168 Tx HO Ring Port - Configuration (RW) ....................................................................................................... 318
169 Tx HO Ring Port - Counter Configuration (RW) ......................................................................................... 319
170 Tx HO Ring Port - Event Latch (COW-1) ................................................................................................... 319
171 Tx HO Ring Port - Performance Counters (RW) ........................................................................................ 319
172 Tx HO Ring Port - Performance Counter Shadow Registers (RO) ............................................................ 319
173 Tx HO Ring Port - Defects ......................................................................................................................... 319
174 Tx HO Ring Port - Interrupt Mask (RW) ..................................................................................................... 320
175 Tx HO Ring Port - General Interrupt (RO) .................................................................................................. 320
176 Tx HO Ring Port - Defect Interrupt (RO) .................................................................................................... 320
177 HO POH Monitor - Received-64 Byte Trace Message (RO) ...................................................................... 320
178 HO POH Monitor - Received 16-Byte Trace Message (RO) ...................................................................... 321
179 HO POH Monitor - Accepted Bytes (RO) ................................................................................................... 321
180 HO POH Monitor - Expected J1 Bytes (RW) .............................................................................................. 321
181 HO POH Monitor - Expected C2 Bytes (RW) ............................................................................................. 321
182 HO POH Monitor - Received POH Bytes (RO) .......................................................................................... 321
183 HO POH Monitor - Accepted POH Bytes (RO) .......................................................................................... 322
184 HO POH Monitor - Configuration (RW) ...................................................................................................... 322
185 HO POH Monitor - Loopback Control (RW) ............................................................................................... 322
186 HO POH Monitor - Channel Configuration (RW) ........................................................................................ 322
187 HO POH Monitor - Channel Status (RO) ................................................................................................... 324
188 HO POH Monitor - Channel Defects (RO) ................................................................................................. 324
189 HO POH Monitor - J1 Message Status (RO) ............................................................................................. 324
190 HO POH Monitor - Defects (RO) ................................................................................................................ 325
191 HO POH Monitor - Latched Defects (R/COW-1) ........................................................................................ 325
192 HO POH Monitor - Defect Masks (RW) ...................................................................................................... 326
193 HO POH Monitor - Defects Latched For PMFM (R/COW-0) ...................................................................... 326
194 HO POH Monitor - Defects PM (RO) ......................................................................................................... 327
195 HO POH Monitor - Defects FM (RO) .......................................................................................................... 327
196 HO POH Monitor - Defect Configuration (RW) ........................................................................................... 328
197 HO POH Monitor - Defect Summary (RO) ................................................................................................. 328
198 HO POH Monitor - Defect Summary Mask (RW) ....................................................................................... 329
199 HO POH Monitor - Defect Group Summary (RO) ...................................................................................... 329
200 HO POH Monitor - APS Event (RO) ........................................................................................................... 329
201 HO POH Monitor - Latched APS Event (R/COW-1) ................................................................................... 329
202 HO POH Monitor - APS Event Mask (RW) ................................................................................................ 329
203 HO POH Monitor - APS Interrupt (RO) ...................................................................................................... 330
- 11 of 402 -
PRELIMINARY TXC-04236-MB, Ed. 3
July 2004
11 Page | ||
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| PDF Descargar | [ Datasheet TXC04236.PDF ] | |
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