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PM25LV010 데이터시트 PDF




Programmable Microelectronics에서 제조한 전자 부품 PM25LV010은 전자 산업 및 응용 분야에서
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부품번호 PM25LV010 기능
기능 (PM25LV010 / PM25LV512) Serial Flash Memory
제조업체 Programmable Microelectronics
로고 Programmable Microelectronics 로고


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PM25LV010 데이터시트, 핀배열, 회로
PMC
Pm25LV512 / Pm25LV010
512 Kbit / 1 Mbit 3.0 Volt-only, Serial Flash Memory
With 25 MHz SPI Bus Interface
FEATURES
• Single Power Supply Operation
- Low voltage range: 2.7 V - 3.6 V
• Block Write Protection
- The Block Protect (BP1, BP0) bits allow part or entire
of the memory to be configured as read-only.
• Memory Organization
- Pm25LV512: 64K x 8 (512 Kbit)
• Hardware Data Protection
- Pm25LV010: 128K x 8 (1 Mbit)
- Write Protect (WP#) pin will inhibit write operations
to the status register
• Cost Effective Sector/Block Architecture
- Uniform 4 Kbyte sectors
m- Uniform 32 Kbyte blocks (8 sectors per block)
o- Two blocks with 32 Kbytes each (512 Kbit)
- Four blocks with 32 Kbytes each (1 Mbit)
.c- 128 pages per block
• Serial Peripheral Interface (SPI) Compatible
U- Supports SPI Modes 0 (0,0) and 3 (1,1)
t4• High Performance Read
- 25 MHz clock rate (maximum)
e• Page Mode for Program Operations
She- 256 bytes per page
Page Program (up to 256 Bytes)
- Typical 2 ms per page program time
Sector, Block and Chip Erase
- Typical 40 ms sector/block/chip erase time
• Single Cycle Reprogramming for Status Register
- Build-in erase before programming
• High Product Endurance
- Guarantee 100,000 program/erase cycles per single
sector (preliminary)
- Minimum 20 years data retention
• Industrial Standard Pin-out and Package
- 8-pin JEDEC SOIC
- 8-contact WSON
- Optional lead-free (Pb-free) packages
taGENERAL DESCRIPTION
aThe Pm25LV512/010 are 512 Kbit/1 Mbits 3.0 Volt-only serial Flash memories. These devices are designed to use
.Da single low voltage, range from 2.7 Volt to 3.6 Volt, power supply to perform read, erase and program operations.
The devices can be programmed in standard EPROM programmers as well.
wThe device is optimized for use in many commercial applications where low-power and low-voltage operation are
essential. The Pm25LV512/010 is enabled through the Chip Enable pin (CE#) and accessed via a 3-wire interface
wconsisting of Serial Data Input (Sl), Serial Data Output (SO), and Serial Clock (SCK). All write cycles are com-
wpletely self-timed.
Block Write protection for top 1/4, top 1/2 or the entire memory array (1M) or entire memory array (512K) is enabled
by programming the status register. Separate write enable and write disable instructions are provided for additional
data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts
to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial
sequence.
The Pm25LV512/010 are manufactured on PMC’s advanced nonvolatile CMOS technology, P-FLASH™. The de-
vices are offered in 8-pin JEDEC SOIC and 8-contact WSON packages with operation frequency up to 25 MHz.
Programmable Microelectronics Corp. 1 Issue Date: February, 2004, Rev: 1.4




PM25LV010 pdf, 반도체, 판매, 대치품
PMC
BLOCK DIAGRAM
Pm25LV512/010
SPI Chip Block Diagram
Control Logic
High Voltage
Generator
Instruction Decoder
Serial /Parallel convert Logic
Address Latch
& Counter
2KBit Page Buffer
Status
Register
Memory Array
X-DECODER
Programmable Microelectronics Corp.
4
Issue Date: February, 2004, Rev: 1.4

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PM25LV010 전자부품, 판매, 대치품
PMC
Pm25LV512/010
DEVICE OPERATION
The Pm25LV512/010 is designed to interface directly with the synchronous serial peripheral interface (SPI) of the
6800 type series of microcontrollers.
The Pm25LV512/010 utilizes an 8-bit instruction register. The list of instructions and their operation codes are
contained in Table 1. All instructions, addresses, and data are transferred with the MSB first and start with a high-
to-low transition.
Write is defined as program and/or erase in this specification. The following commands, PAGE PROGRAM,
SECTOR ERASE, BLOCK ERASE, CHIP ERASE, and WRSR are write instructions for Pm25LV512/010.
Table 1. Instruction Set for the Pm25LV512/010
Instruction Name
WREN
WRDI
RDSR
WRSR
READ
FAST_READ
PG_ PROG
SECTOR_ERASE
BLOCK_ERASE
CHIP_ERASE
RDID
Instruction Format
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 1011
0000 0010
1101 0111
1101 1000
1100 0111
1010 1011
Hex Code Operation
06h
04h
05h
01h
03h
0Bh
02h
D7h
D8h
C7h
ABh
Set Write Enable Latch
Reset Write Enable Latch
Read Status register
Write Status Register
Read Data from Memory Arrary
Read Data from Memory at Higher Speed
Program Data Into Memory Array
Erase One Sector in Memory Array
Erase One Block in Memory Array
Erase Entire Memory Array
Read Manufacturer and Product ID
READ PRODUCT ID (RDID): The RDID instruction allows the user to read the manufacturer and product ID of the
device. The instruction code is followed by three dummy bytes, each bit being latched-in on Serial Data Input (SI)
during the rising edge of Serial Clock (SCK). Then the first manufacturer ID (9Dh) is shifted out on Serial Data
Output (SO), followed by the device ID (7Bh = Pm25LV512; 7Ch = Pm25LV010) and the second manufacturer ID
(7Fh), each bit been shifted out during the falling edge of Serial Clock (SCK).
Table 2. Product Identification
Product Identification
Manufacturer ID
Device ID:
Pm25LV512
Pm25LV010
Data
9Dh
7Bh
7Ch
Programmable Microelectronics Corp.
7
Issue Date: February, 2004, Rev: 1.4

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