|
|
PDF MT58L1MY18D Data sheet ( Hoja de datos )
| Número de pieza | MT58L1MY18D | |
| Descripción | (MT58xxxx) 16Mb SYNCBURST SRAM | |
| Fabricantes | Micron Technology | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MT58L1MY18D (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
ADVANCE
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
16Mb SYNCBURST™
SRAM
MT58L1MY18D, MT58V1MV18D,
MT58L512Y32D, MT58V512V32D,
MT58L512Y36D, MT58V512V36D
3.3V VDD, 3.3V or 2.5V I/O; 2.5V VDD, 2.5V
I/O, Pipelined, Double-Cycle Deselect
FEATURES
• Fast clock and OE# access times
• Single +3.3V ±0.165Vor 2.5V ±0.125V power supply
(VDD)
• Separate +3.3V or 2.5V isolated output buffer
supply (VDDQ)
• SNOOZE MODE for reduced-power standby
• Common data inputs and data outputs
• Individual BYTE WRITE control and GLOBAL
WRITE
• Three chip enables for simple depth expansion and
address pipelining
• Clock-controlled and registered addresses, data I/Os
and control signals
• Internally self-timed WRITE cycle
• Burst control (interleaved or linear burst)
• Automatic power-down
• 100-pin TQFP package
• 165-pin FBGA package
• Low capacitive bus loading
• x18, x32, and x36 versions available
OPTIONS
TQFP MARKING*
• Timing (Access/Cycle/MHz)
3.5ns/6ns/166 MHz
-6
4.0ns/7.5ns/133 MHz
-7.5
5ns/10ns/100 MHz
-10
• Configurations
3.3V VDD, 3.3V or 2.5V I/O
1 Meg x 18
512K x 32
512K x 36
2.5V VDD, 2.5V I/O
1 Meg x 18
512K x 32
512K x 36
MT58L1MY18D
MT58L512Y32D
MT58L512Y36D
MT58V1MV18D
MT58V512V32D
MT58V512V36D
• Packages
100-pin TQFP (3-chip enable)
165-pin FBGA
T
F
• Operating Temperature Range
Commercial (0ºC to +70ºC)
None
*See page 34 for FBGA package marking guide.
Part Number Example:
MT58L1MY18DT-7.5
100-Pin TQFP1
165-Pin FBGA
(Preliminary Package Data)
NOTE: 1. JEDEC-standard MS-026 BHA (LQFP).
GENERAL DESCRIPTION
The Micron® SyncBurst™ SRAM family employs high-
speed, low-power CMOS designs that are fabricated
using an advanced CMOS process.
Micron’s 16Mb SyncBurst SRAMs integrate a 1 Meg x
18, 512K x 32, or 512K x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst
counter. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single-clock in-
put (CLK). The synchronous inputs include all addresses,
all data inputs, active LOW chip enable (CE#), two
additional chip enables for easy depth expansion (CE2,
CE2#), burst control inputs (ADSC#, ADSP#, ADV#),
byte write enables (BWx#) and global write (GW#). Note
that CE2# is not available on the T Version.
Asynchronous inputs include the output enable
(OE#), clock (CLK) and snooze enable (ZZ). There is also
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
MT58L1MY18D_2.p65 – Rev 7/00
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
1 page  
ADVANCE
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
TQFP PIN DESCRIPTIONS
x18
37
36
32-35, 42-50,
80-82, 99,
100
93
94
–
–
87
88
89
98
92
64
97
86
83
x32/x36
37
36
32-35, 42-50,
81, 82, 99,
100
93
94
95
96
87
88
89
98
92
64
97
86
83
SYMBOL
SA0
SA1
SA
BWa#
BWb#
BWc#
BWd#
BWE#
GW#
CLK
CE#
CE2#
ZZ
CE2
OE#
(G#)
ADV#
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
DESCRIPTION
Synchronous Address Inputs: These inputs are registered and must
meet the setup and hold times around the rising edge of CLK.
Synchronous Byte Write Enables: These active LOW inputs allow
individual bytes to be written and must meet the setup and hold
times around the rising edge of CLK. A byte write enable is LOW
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQa pins and DQPa; BWb# controls DQb pins and
DQPb. For the x32 and x36 versions, BWa# controls DQa pins and
DQPa; BWb# controls DQb pins and DQPb; BWc# controls DQc pins
and DQPc; BWd# controls DQd pins and DQPd. Parity is only
available on the x18 and x36 versions.
Byte Write Enable: This active LOW input permits BYTE WRITE
operations and must meet the setup and hold times around the
rising edge of CLK.
Global Write: This active LOW input allows a full 18-, 32-, or 36-bit
WRITE to occur independent of the BWE# and BWx# lines and
must meet the setup and hold times around the rising edge of
CLK.
Clock: This signal registers the address, data, chip enable, byte
write enables and burst control inputs on its rising edge. All
synchronous inputs must meet setup and hold times around the
clock’s rising edge.
Synchronous Chip Enable: This active LOW input is used to enable
the device and conditions the internal use of ADSP#. CE# is
sampled only when a new external address is loaded.
Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is
loaded.
Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored. This pin has an internal pull-down and can be floating.
Synchronous Chip Enable: This active HIGH input is used to enable
the device and is sampled only when a new external address is
loaded.
Output Enable: This active LOW, asynchronous input enables the
data I/O output drivers. G# is the JEDEC-standard term for OE#.
Synchronous Address Advance: This active LOW input is used to
advance the internal burst counter, controlling burst access after
the external address is loaded. A HIGH on this pin effectively
causes wait states to be generated (no address advance). To ensure
use of correct address during a WRITE cycle, ADV# must be HIGH at
the rising edge of the first clock after an ADSP# cycle is initiated.
(continued on next page)
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
MT58L1MY18D_2.p65 – Rev 7/00
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
5 Page 
ADVANCE
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH)
FIRST ADDRESS (EXTERNAL)
X...X00
X...X01
X...X10
X...X11
SECOND ADDRESS (INTERNAL)
X...X01
X...X00
X...X11
X...X10
THIRD ADDRESS (INTERNAL)
X...X10
X...X11
X...X00
X...X01
FOURTH ADDRESS (INTERNAL)
X...X11
X...X10
X...X01
X...X00
LINEAR BURST ADDRESS TABLE (MODE = LOW)
FIRST ADDRESS (EXTERNAL)
X...X00
X...X01
X...X10
X...X11
SECOND ADDRESS (INTERNAL)
X...X01
X...X10
X...X11
X...X00
THIRD ADDRESS (INTERNAL)
X...X10
X...X11
X...X00
X...X01
FOURTH ADDRESS (INTERNAL)
X...X11
X...X00
X...X01
X...X10
PARTIAL TRUTH TABLE FOR WRITE COMMANDS (x18)
FUNCTION
READ
READ
WRITE Byte “a”
WRITE Byte “b”
WRITE All Bytes
WRITE All Bytes
GW#
H
H
H
H
H
L
BWE#
H
L
L
L
L
X
BWa#
X
H
L
H
L
X
BWb#
X
H
H
L
L
X
PARTIAL TRUTH TABLE FOR WRITE COMMANDS (x32/x36)
FUNCTION
READ
READ
WRITE Byte “a”
WRITE All Bytes
WRITE All Bytes
GW#
H
H
H
H
L
BWE#
H
L
L
L
X
BWa#
X
H
L
L
X
BWb#
X
H
H
L
X
BWc#
X
H
H
L
X
BWd#
X
H
H
L
X
NOTE: Using BWE# and BWa# through BWd#, any one or more bytes may be written.
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
MT58L1MY18D_2.p65 – Rev 7/00
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MT58L1MY18D.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MT58L1MY18D | (MT58xxxx) 16Mb SYNCBURST SRAM | Micron Technology |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |