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IZ4442 데이터시트 PDF




IK Semiconductor에서 제조한 전자 부품 IZ4442은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 IZ4442 기능
기능 Intelligent 256 byte EEPROM with wirte protect function & security logic
제조업체 IK Semiconductor
로고 IK Semiconductor 로고


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IZ4442 데이터시트, 핀배열, 회로
m TECHNICAL DATA
U.coINTELLIGENT 256-BYTE EEPROM WITH WRITE PROTECT
et4FUNCTION AND PROGRAMMABLE SECURITY CODE (PSC)
SheFeatures
ta256 x 8-bit EEPROM organization
aByte-wise addressing
.DIrreversible byte-wise write protection of lowest
w32 addresses (Byte 0...31)
w32 x 1-bit organization of protection memory
w Two-wire link protocol
End of processing indicated at data output
Answer-to-Reset ace. to ISO standard 7816-3
mProgramming time 2.5 ms per byte for both erasing
and writing
oMinimum of 104 write/erase cycles1)
Data retention for minimum of ten years1)
.cContact configuration and serial interface in accordance
with ISO standard 7816 (synchronous transmission)
UAdditional Feature of IZE4442
t4Data can only be changed after entry of the correct 3-byte programmable security code (security
memory)
eType
Ordering Code
Package
eIZE4442 M2.2
on request
Wire-Bonded Module M2.2
IZE4442 C
on request
Chip
hIZE4442 M2.2
on request
Wire-Bonded Module M2.2
IZE4442 C
on request
Chip
S1) Values are temperature dependent, for further information please refer to your sales office.
taPin Configuration(top view)
a(Card Contacts)Pin Definitions and Functions
.DCard Contact
C1
C2
wC3
C4
wC5
wC6
Symbol
VCC
RST
CLK
N.C.
GND
N.C.
Function
Supply voltage
Reset
Clock input
Not connected
Ground
Not connected
C7 I/O Bi-directional data line
(open drain)
omC8
N.C.
Not connected
.cIZE4442 comes as a M2.2 wire-bonded module for embedding in plastic cards or as a die for
www.DataSheet4Ucustomer packaging.
1




IZ4442 pdf, 반도체, 판매, 대치품
IZ4442
The transmission protocol consists of the 4 modes:
- Reset and Answer-to-Reset
- Command Mode
- Outgoing Data Mode
- Processing Mode
Operational modes
Note: The I/O pin is open drain and therefore requires an external pull up resistor to achieve a high
level.
Reset and Answer-to-Reset
Answer-to-Reset takes place according to ISO standard 7816-3 (ATR). The reset can be given at any
time during operation. In the beginning, the address counter is set to zero together with a clock pulse
and the first data bit (LSB) is output to I/O when RST is set from level H to level L. Under a continuous
input of additional 31 clock pulses the contents of the first 4 EEPROM addresses is read out. The
33rd clock pulse switches I/O to high impedance Z and finishes the ATR procedure.
Answer-to-Reset (Hex)
Byte 1
Byte 2
DO7...DO0
DO15... DO8
Byte 3
D023...D016
Byte 4
DO31 ...DO24
Figure 2 Reset and Answer-to-Reset
Operational Modes
Command Mode
After the Answer-to-Reset the chip waits for a command. Every command begins with a start
condition, includes a 3 bytes long command entry followed by an additional clock pulse and ends with
a stop condition.
- Start condition: Falling edge on I/O during CLK in level H
- Stop condition: Rising edge on I/O during CLK in level H
After the reception of a command there are two possible modes:
- Outgoing data mode for reading
- Processing mode for writing and erasing
Outgoing Data Mode
In this mode the 1C sends data to the IFD. The first bit becomes valid on I/O after the first falling edge
on CLK. After the last data bit an additional clock pulse is necessary in order to set I/O to high
impedance Z and to prepare the 1C for a new command entry. During this mode any start and stop
condition is discarded.
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IZ4442 전자부품, 판매, 대치품
IZ4442
2.3.1 Read Main Memory
The command reads out the contents of the main memory (with LSB first) starting at the given byte
address (N = 0 ... 255) up to the end of the memory. After the command entry the IFD has to supply
sufficient clock pulses. The number of clocks is m = (256 - N) x 8 + 1. The read access to the main
memory is always possible.
Address
(decimal)
255
32
31
3
2
1
0
Main Memory
Data Byte 255 (D7...D0)
:
:
:
Data Byte 32 (D7...D0)
Data Byte 31 (D7...D0)
:
:
:
Data Byte 3 (D7...D0)
Data Byte 2 (D7...D0)
Data Byte 1 (D7...D0)
Data Byte 0 (D7...D0)
Protection Memory
-
-
Protection Bit 31 (D31)
Protection Bit 3 (D3)
Protection Bit 2 (D2)
Protection Bit 1 (D1)
Protection Bit 0 (D0)
Security Memory
-
-
-
Reference Data Byte 3 (D7...D0)
Reference Data Byte 2 (D7...D0)
Reference Data Byte 1 (D7...D0)
Error Counter
Command: READ MAIN MEMORY
Control
Address
Data
B7 B6 B5 B4 B3 B2 B1 B0 A7...A0
D7...D0
Binary
0 0 1 1 0 0 0 0 Address No effect
Hexadecimal
30H
00H...FFH No effect
Figure 5 Read Main Memory
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IZ4442

Intelligent 256 byte EEPROM with wirte protect function & security logic

IK Semiconductor
IK Semiconductor

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