PDF CY7C455 Data sheet ( Hoja de datos )

Número de pieza	CY7C455
Descripción	(CY7C455 - CY7C457) Cascadable Colcked FIFOs
Fabricantes	Cypress Semiconductor
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No Preview Available ! 57 CY7C455 CY7C456 CY7C457 512 x 18, 1K x 18, and 2K x 18 Cascadable Clocked FIFOs with Programmable Flags Features • High-speed, low-power, first-in first-out (FIFO) memories • 512 x 18 (CY7C455) • 1,024 x 18 (CY7C456) • 2,048 x 18 (CY7C457) • 0.65 micron CMOS for optimum speed/power • High-speed 83-MHz operation (12 ns read/write cycle time) • Low power — ICC=90 mA • Fully asynchronous and simultaneous read and write operation • Empty, Full, Half Full, and programmable Almost Empty and Almost Full status flags • TTL compatible • Retransmit function • Parity generation/checking • Output Enable (OE) pins • Independent read and write enable pins • Center power and ground pins for reduced noise • Supports free-running 50% duty cycle clock inputs • Width Expansion Capability • Depth Expansion Capability • 52-pin PLCC and 52-pin PQFP Functional Description The CY7C455, CY7C456, and CY7C457 are high-speed, low-power, first-in first-out (FIFO) memories with clocked read and write interfaces. All are 18 bits wide. The CY7C455 has a 512-word memory array, the CY7C456 has a 1,024-word memory array, and the CY7C457 has a 2,048-word memory array. The CY7C455, CY7C456, and CY7C457 can be cas- caded to increase FIFO depth. Programmable features in- clude Almost Full/Empty flags and generation/checking of par- ity. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multi- processor interfaces, and communications buffering. These FIFOs have 18-bit input and output ports that are con- trolled by separate clock and enable signals. The input port is controlled by a free-running clock (CKW) and a write enable pin (ENW). Logic Block Diagram D0 – 17 INPUT REGISTER CKW ENW WRITE CONTROL PARITY MR FL/RT XI WRITE POINTER RESET LOGIC EXPANSION LOGIC RETRANSMIT LOGIC RAM ARRAY 512 x 18 1024 x 18 2048 x 18 THREE–STATE OUTPUT REGISTER OE Q0 – 7, Q8/PG1/PE1 Q9– 16, Q17/PG2/PE2 Pin Configurations PLCC Top View FLAG/PARITY PROGRAM REGISTER FLAG LOGIC READ POINTER D2 D1 D0 XI HF ENW E/F CKW PAFE/XO HF E/F XO/PAFE Q0 Q1 Q2 Q3 7 6 5 4 3 2 1 52 51 50 49 48 47 8 46 9 45 10 44 11 43 12 42 13 7C455 41 14 7C456 40 15 7C457 39 16 38 17 37 18 36 19 35 20 34 21 22 23 24 25 26 27 28 29 30 31 32 33 D13 D14 D15 D16 D17 FL/RT MR CKR ENR OE Q17/PG2/PE2 Q16 Q15 READ CONTROL CKR ENR c455-1 c455-2 www.DataSheet4U.com Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 wwDwo.DcautmaSehnete#t4: U3.8c-o0m6003 Rev. A Revised December 26, 2002 www.DataSheet4U.com 1 page CY7C455 CY7C456 CY7C457 Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH[3] VIL[3] IIX IOS[4] IOZL IOZH ICC1[5] ICC2[6] ISB[7] Description Test Conditions Output HIGH Voltage VCC = Min., IOH = –2.0 mA Output LOW Voltage VCC = Min., IOL = 8.0 mA Input HIGH Voltage Input LOW Voltage Input Leakage Current VCC = Max. Output Short Circuit Current VCC = Max., VOUT = GND Output OFF, High Z OE > VIH, VSS < VO < VCC Current Operating Current VCC = Max., IOUT = 0 mA Com’l Ind Operating Current VCC = Max., IOUT = 0 mA Com’l Ind Standby Current VCC = Max., IOUT = 0 mA Com’l Ind 7C455/6/7– 12 Min. Max 2.4 0.4 2.2 –0.5 –10 VCC 0.8 +10 –90 –10 +10 160 180 90 100 40 40 7C455/6/7– 7C455/6/7– 7C455/6/7– 14 20 30 Min. Max Min. Max Min. Max 2.4 2.4 2.4 0.4 0.4 0.4 2.2 VCC 2.2 VCC 2.2 VCC –0.5 0.8 –0.5 0.8 –0.5 0.8 –10 +10 –10 +10 –10 +10 –90 –90 –90 –10 +10 –10 +10 –10 +10 160 140 120 180 160 140 90 90 90 100 100 100 40 40 40 40 40 40 Unit V V V V µA mA µA mA mA mA mA mA mA Capacitance[8] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 10 12 Unit pF pF AC Test Loads and Waveforms[9, 10, 11, 12, 13] 5V OUTPUT R1 500Ω CL INCLUDING JIG AND SCOPE R2 333Ω c455-4 3.0V GND ≤ 3 ns ALL INPUT PULSES 90% 10% 90% 10% ≤ 3 ns c455-5 Equivalent to: THÉVENIN EQUIVALENT 200Ω OUTPUT 2V Notes: 3. The VIH and VIL specifications apply for all inputs except XI. The XI pin is not a TTL input. It is connected to either XO of the previous device or VSS. 4. Test no more than one output at a time for not more than one second. 5. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at maximum frequency (fMAX), while data inputs switch at fMAX/2. Outputs are unloaded. 6. Input signals switch from 0V to 3V with a rise/fall time less than 3 ns, clocks and clock enables switch at 20 MHz, while the data inputs switch at 10 MHz. Outputs are unloaded. 7. All input signals are connected to VCC. All outputs are unloaded. Read and write clocks switch at maximum frequency (fMAX). 8. Tested initially and after any design or process changes that may affect these parameters. 9. CL = 30 pF for all AC parameters except for tOHZ. 10. CL = 5 pF for tOHZ. 11. All AC measurements are referenced to 1.5V except tOE, tOLZ, and tOHZ. 12. tOE and tOLZ are measured at ± 100 mV from the steady state. 13. tOHZ is measured at +500 mV from VOL and – 500 mV from VOH. Document #: 38-06003 Rev. A Page 5 of 23 5 Page CY7C455 CY7C456 CY7C457 Switching Waveforms (continued) Write to Half Full Timing Diagram with Free-Running Clocks[22, 30, 31, 32] COUNT 1024 [512] [256] 1025 [513] [257] 1024 [512] [256] 1023 [511] [255] 1024 [512] [256] CKW W1 ENABLED WRITE W2 W3 W4 ENABLED WRITE ENW CKR ENR HF tSKEW1 R1 R2 ENABLED READ tFD tSKEW2 R3 ENABLED READ R4 tFD 1025 [513] [257] W5 ENABLED WRITE R5 tFD 1026 [514] [258] W6 ENABLED WRITE R6 E/F PAFE HIGH HIGH c455-15 Write to Half Full Timing Diagram with Write Flag Update Cycle with Free-Running Clocks[22, 30, 31, 32, 33, 34] 1024 COUNT [512] [256] 1025 [513] [257] 1024 [512] [256] 1023 [511] [255] 1023 [511] [255] (no change) FLAG UPDATE CYCLE 1024 [512] [256] 1025 [513] [257] 1026 [514] [258] CKW W1 ENABLED WRITE W2 W3 W4 W5 W6 W7 FLAG ENABLED ENABLED ENABLED UPDATE WRITE WRITE WRITE WRITE ENW tSKEW1 tSKEW2 CKR R1 R2 ENABLED R3 ENABLED R4 R5 R6 R7 READ READ ENR tFD HF tFD tFD E/F HIGH PAFE HIGH c455–16 Notes: 30. CKW is clock and CKR is opposite clock. 31. Count = 1,025 indicates Half Full for the CY7C446 and CY7C456. Count = 513 indicates Half Full for the CY7C447 and CY7C457. Count = 257 indicates Half Full for the CY7C448 and CY7C458. 32. When the FIFO contains 1,024 [512] [256] words, the rising edge of the next enabled write causes the HF to be true (LOW). 33. The HF write flag update cycle does not affect the count because ENW is HIGH. It only updates HF to HIGH. 34. When making the transition from Half Full to Less Than Half Full, the count must decrease by two (i.e., 1,025 Á1,023; two enabled reads: R2 and R3) before a write (W4) can update flags to less than Half Full. Document #: 38-06003 Rev. *A Page 11 of 23 11 Page

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