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A1010B PDF 데이터시트 ( Data , Function )

부품번호 A1010B 기능
기능 (A1010B / A1020B) FPGAs
제조업체 Actel Corporation
로고 Actel Corporation 로고 



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A1010B 데이터시트, 핀배열, 회로
www.DataSheet4U.com
ACT1 Series FPGAs
Features
• 5V and 3.3V Families fully compatible with JEDEC
specifications
• Up to 2000 Gate Array Gates (6000 PLD equivalent gates)
• Replaces up to 50 TTL Packages
• Replaces up to twenty 20-Pin PAL® Packages
• Design Library with over 250 Macro Functions
• Gate Array Architecture Allows Completely Automatic
Place and Route
• Up to 547 Programmable Logic Modules
• Up to 273 Flip-Flops
• Data Rates to 75 MHz
• Two In-Circuit Diagnostic Probe Pins Support Speed
Analysis to 25 MHz
• Built-In High Speed Clock Distribution Network
• I/O Drive to 10 mA (5 V), 6 mA (3.3 V)
• Nonvolatile, User Programmable
• Fabricated in 1.0 micron CMOS technology
Description
The ACT™ 1 Series of field programmable gate arrays
(FPGAs) offers a variety of package, speed, and application
combinations. Devices are implemented in silicon gate,
1-micron two-level metal CMOS, and they employ Actel’s
PLICE® antifuse technology. The unique architecture offers
gate array flexibility, high performance, and instant
turnaround through user programming. Device utilization is
typically 95 to 100 percent of available logic modules.
ACT 1 devices also provide system designers with unique
on-chip diagnostic probe capabilities, allowing convenient
testing and debugging. Additional features include an on-chip
mclock driver with a hardwired distribution network. The
.conetwork provides efficient clock distribution with minimum
skew.
t4UThe user-definable I/Os are capable of driving at both TTL
eand CMOS drive levels. Available packages include plastic
eand ceramic J-leaded chip carriers, ceramic and plastic quad
hflatpacks, and ceramic pin grid array.
w.DataSApril 1996
ww © 1996 Actel Corporation
A security fuse may be programmed to disable all further
programming and to protect the design from being copied or
reverse engineered.
Product Family Profile
Device
A1010B A1020B
A10V10B A10V20B
Capacity
Gate Array Equivalent Gates
PLD Equivalent Gates
TTL Equivalent Packages
20-Pin PAL Equivalent Packages
1,200
3,000
30
12
2,000
6,000
50
20
Logic Modules
295 547
Flip-Flops (maximum)
147 273
Routing Resources
Horizontal Tracks/Channel
Vertical Tracks/Column
PLICE Antifuse Elements
22
13
112,000
22
13
186,000
User I/Os (maximum)
57 69
Packages:
44 PLCC 44 PLCC
68 PLCC 68 PLCC
84 PLCC
100 PQFP 100 PQFP
80 VQFP 80 VQFP
84 CPGA 84 CPGA
84 CQFP
Performance
5 V Data Rate (maximum)
3.3 V Data Rate (maximum)
75 MHz
55 MHz
75 MHz
55 MHz
Note: See Product Plan on page 1-286 for package availability.
The Designer and Designer
Advantage™ Systems
The ACT 1 device family is supported by Actel’s Designer and
Designer Advantage Systems, allowing logic design
implementation with minimum effort. The systems offer
Microsoft® Windowsand X Windowsgraphical user
interfaces and integrate with the resident CAE system to
provide a complete gate array design environment: schematic
capture, simulation, fully automatic place and route, timing
verification, and device programming. The systems also
include the ACTmapVHDL optimization and synthesis tool
and the ACTgenMacro Builder, a powerful macro function
generator for counters, adders, and other structural blocks.
1-283




A1010B pdf, 반도체, 판매, 대치품
www.DataSheet4U.com
Product Plan
Speed Grade*
Application
Std –1 –2 –3
C I MB
A1010B Device
44-pin Plastic Leaded Chip Carrier (PL)
68-pin Plastic Leaded Chip Carrier (PL)
100-pin Plastic Quad Flatpack (PQ)
80-pin Very Thin (1.0 mm) Quad Flatpack (VQ)
84-pin Ceramic Pin Grid Array (PG)
——
——
——
——
———
A1020B Device
44-pin Plastic Leaded Chip Carrier (PL)
68-pin Plastic Leaded Chip Carrier (PL)
84-pin Plastic Leaded Chip Carrier (PL)
100-pin Plastic Quad Flatpack (PQ)
80-pin Very Thin (1.0 mm) Quad Flatpack (VQ)
84-pin Ceramic Pin Grid Array (PG)
84-pin Ceramic Quad Flatpack (CQ)
——
——
——
——
——
——
———
A10V10B Device
68-pin Plastic Leaded Chip Carrier (PL)
80-pin Very Thin (1.0 mm) Quad Flatpack (VQ)
———
———
———
———
A10V20B Device
68-pin Plastic Leaded Chip Carrier (PL)
84-pin Plastic Leaded Chip Carrier (PL)
80-pin Very Thin (1.0 mm) Quad Flatpack (VQ)
———
———
———
———
———
———
Applications: C = Commercial Availability: = Available * Speed Grade: –1 = Approx. 15% faster than Standard
I = Industrial
P = Planned
–2 = Approx. 25% faster than Standard
M = Military
— = Not Planned
–3 = Approx. 35% faster than Standard
B = MIL-STD-883
Device Resources
User I/Os
Device
A1010B, A10V10B
A1020B, A10V20B
Logic Modules
295
547
Gates
1200
2000
44-pin
34
34
68-pin
57
57
80-pin
57
69
84-pin
57
69
100-pin
57
69
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A1010B 전자부품, 판매, 대치품
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ACT1 Series FPGAs
Package Thermal Characteristics
The device junction to case thermal characteristics is
θjc, and the junction to ambient air characteristics is θja. The
thermal characteristics for θja are shown with two different
air flow rates. Maximum junction temperature is 150°C.
A sample calculation of the maximum power dissipation for
an 84-pin plastic leaded chip carrier at commercial
temperature is as follows:
M------a---x------j--u---n---c----t--i--o---n-----t--e---m-----p---.--(---°--θC---j--)a---(–--°---MC------a--W-x-----c)---o---m-----m-----e---r--c----i--a---l---t--e---m-----p----.--(--°---C----)- = -1--5---0-3---7°---C°---C--–-----7-W--0---°---C-- = 2.2 W
Package Type
Plastic J-Leaded Chip Carrier
Plastic Quad Flatpack
Very Thin (1.0 mm) Quad Flatpack
Ceramic Pin Grid Array
Ceramic Quad Flatpack
Pin Count
44
68
84
100
80
84
84
θjc
15
13
12
13
12
8
5
θja
Still Air
45
38
37
48
43
33
40
θja
300 ft/min
35
29
28
40
35
20
30
Units
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
General Power Equation
P = [ICCstandby + ICCactive] * VCC + IOL * VOL * N + IOH *
(VCC – VOH) * M
Where:
ICCstandby is the current flowing when no inputs or
outputs are changing.
ICCactive is the current flowing due to CMOS switching.
IOL, IOH are TTL sink/source currents.
VOL, VOH are TTL level output voltages.
N equals the number of outputs driving TTL loads to
VOL.
M equals the number of outputs driving TTL loads to
VOH.
An accurate determination of N and M is problematical
because their values depend on the family type, design
details, and on the system I/O. The power can be divided into
two components: static and active.
omStatic Power Component
.cActel FPGAs have small static power components that result
Uin lower power dissipation than PALs or PLDs. By integrating
t4multiple PALs/PLDs into one FPGA, an even greater
www.DataSheereduction in board-level power dissipation can be achieved.
The power due to standby current is typically a small
component of the overall power. Standby power is calculated
below for commercial, worst case conditions.
ICC
3 mA
VCC
5.25 V
Power
15.75 mW (max)
1 mA
5.25 V
5.25 mW (typ)
0.75 mA
3.60 V
2.70 mW (max)
0.30 mA
3.30 V
0.99 mW (typ)
Active Power Component
Power dissipation in CMOS devices is usually dominated by
the active (dynamic) power dissipation. This component is
frequency dependent, a function of the logic and the
external I/O. Active power dissipation results from charging
internal chip capacitances of the interconnect,
unprogrammed antifuses, module inputs, and module
outputs, plus external capacitance due to PC board traces
and load device inputs. An additional component of the active
power dissipation is the totem-pole current in CMOS
transistor pairs. The net effect can be associated with an
equivalent capacitance that can be combined with frequency
and voltage to represent active power dissipation.
1-289

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A1010B

(A1010B / A1020B) FPGAs

Actel Corporation
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(A1010B / A1020B) FPGAs

Actel Corporation
Actel Corporation

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