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3X8292 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 3X8292
기능 (3X8168 / 3X8292) TARGET SPECIFICATION ELECTRICAL DATA
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3X8292 데이터시트, 핀배열, 회로
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FRONTEND 4049 FM5
3x8168; 3x8292
TARGET SPECIFICATION ELECTRICAL DATA
1. Description:
The frontend 4049 FM5 is specially designed for multimedia applications. It includes TV as well as
FM reception possibility. TV reception standard are B/G; I, D/K, L, L`. The frontend includes a
hyperband tuner which covers the frequency range from 45 to 865 MHz and an IF-part with SAW-
filter, IF-amplifier, video- and sound demodulator. So the AF signal is available at the audio output
terminal, the CVBS signal is available at the video output terminal. Also a 2nd IF output is provided,
which allows external sound demodulation for stereo and NICAM reception. A video buffer is built
in which makes a direct connection to 75 inputs possible. The reception frequency range is
divided in VHF low, VHF high and UHF.
VHFlow part of the tuner is used for FM reception also. Complete FM signal processing including
demodulation and stereo decoding is built in. Baseband signals L (left) and R (right) as well as
MPX (Baseband Multiplex signal) are on pins available.
Band, standard selection and tuning are done via I²C-bus, completely. Also a digital AFC-function
can be realized, because the AFC-voltage generated by the IF-demodulator is fed to an
analogue/digital converter which is integrated in the IF demodulator-IC and readable via I²C-bus.
A DC/DC converter is built in. Therefore supply voltage is 5V only.
2. Mechanical Characteristics:
2.1. Dimensions: according drawing 3x8168GZ
2.2. Weight: appr. 52 g
I²C bus signal SCL
I²C bus signal SDA
Address selection for I²C bus
FM sound output R
FM sound output L
2nd IF
Video output CVBS
Supply voltage VS1
AF sound output / FM MPX
3X8168 ED
November 02
Page: 1/14
8168ED01.DOC




3X8292 pdf, 반도체, 판매, 대치품
6. TV Output parameter:
6.1. Video output:
Conditions:
Standard B/G; Ant. input level 66 dBµV
CVBS - Output level (B/G, D/K, L/L`):
(Standard I):
Load impedance
Video S/N (unweighted):
Flat Field
VHF
UHF
Video sensitivity (Off Air Channels)
Video S/N = 30 dB
Frequency response:
(sin x)/x Ref.: 0.2 MHz
1 MHz
2 MHz
3 MHz
4 MHz
4.43 MHz
5 MHz
sound carrier rejection
B/G
I, D/K, L/L´
Differential gain modulated 5 step staircase
Differential phase modulated 5 step staircase
min. typ.
max. unit
1 Vpp
0.9 Vpp
75
46 dB
47 dB
45 dBµV
-1.5
-2
-4
-4
-5
-12
30
26
3
5
2
3
3
4
3
dB
dB
dB
dB
dB
dB
dB
dB
%pp
°pp
3X8168 ED
November 02
Page: 4/14
8168ED01.DOC

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3X8292 전자부품, 판매, 대치품
8. I²C bus
There are two different I²C bus used one I²C Tuner to control tuning and one I²C IF to control IF
demodulation and baseband processing. With port P0 of control byte 2 the slave address of I2C IF can be
controlled.
8.1 I²C Tuner
8.1.1 Write data format
MSB
LSB
Address byte
1
10
0
0 MA1 MA0 R/W A
Divider byte 1 0 n14 n13 n12 n11 n10 n9 n8 A
Divider byte 2
n7
n6 n5
n4
n3
n2
n1
n0 A
Control byte 1 1 CP T2 T1 T0 RSA RSB OS A
Control byte 2
P7
P6
P5
P4
P3
P2
P1
P0 A
A = Acknowledge
R/W = 0 : Write mode
CP = 1 : charge pump current high
T2, T1, T0 = test bits, normal operation: T2 = 0, T1 = 0, T0 = 1
RSA, RSB bits for minimum step size, see 8.1.2
OS = tuning voltage switch, normal operation: OS = 0
8.1.2 Address selection
MA1
0
0
1
1
MA0
0
1
0
1
Address
C0
C2
C4
C6
Voltage at Pin 11
( 0 to 0.1 ) * VS1
(0.2 to 0.3) * VS1 or open
( 0.4 to 0.6 ) * VS1
( 0.9 to 1 ) * VS1
8.1.3 Oscillator frequency and divider byte calculation:
RSA
RSB
Reference divider
Min. tuning step [kHz]
11
512
62.5
X0
640
50.0
01
1024
31.25
for FM recption we recommend 50 kHz minimum step size
fref [kHz]
7.8125
6.25
3.90625
fOSC= fD + fIF
fIF = 38.9 MHz at B/G, D/K, I, L
fIF = 33.9 MHz at L’
fIF = 33.3 MHz at FM
fOSC : Local oscillator frequency
fD : Desired frequency
fOSC = fREF * 8 * SF
fREF : Crystal reference frequency / 640 = 4 MHz / 640 = 6.25 kHz, ( RSA =X, RSB = 0)
SF : Programmable scaling factor
Scaling factor
SF= 16384* n14 + 8192 * n13 * 4096 * n12 + 2048 * n11 + 1024 * n10 + 512 * n9 + 256* n8 + 128 * n7 +
64 * n6 + 32 * n5 + 16 * n4 + 8 * n3 + 4 * n2 + 2 * n1 + n0
3X8168 ED
November 02
Page: 7/14
8168ED01.DOC

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