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PDF UPD8871 Data sheet ( Hoja de datos )
| Número de pieza | UPD8871 | |
| Descripción | CCD LINEAR IMAGE SENSOR | |
| Fabricantes | NEC | |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD8871
10680 PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR
DESCRIPTION
The µ PD8871 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to
electrical signal and has the function of color separation.
The µ PD8871 has 3 rows of 10680 pixels, and each row has a single-sided readout type of charge transfer register.
And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for 1200 dpi/A4 color
image scanners, color facsimiles and so on.
FEATURES
• Valid photocell : 10680 pixels × 3
• Photocell pitch : 4 µ m
• Photocell size : 4 × 4 µ m2
• Line spacing
• Color filter
: 32 µ m (8 lines) Red line - Green line, Green line - Blue line
: Primary colors (red, green and blue), pigment filter (with light resistance 107 lx•hour)
• Resolution
: 48 dot/mm A4 (210 × 297 mm) size (shorter side)
: 1200 dpi US letter (8.5” × 11”) size (shorter side)
• Drive clock level : CMOS output under 5 V operation
• Data rate
: 10 MHz Max.
• Power supply
• On-chip circuits
::
: +12 V
: Reset feed-through level clamp circuits
Voltage amplifiers
ORDERING INFORMATION
Part Number
Package
µ PD8871CY
CCD linear image sensor 32-pin plastic DIP (10.16 mm (400))
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S15329EJ2V0DS00 (2nd edition)
Date Published September 2002 NS CP (K)
Printed in Japan
The mark shows major revised points.
2001
1 page  
µ PD8871
ABSOLUTE MAXIMUM RATINGS (TA = +25°C)
Parameter
Output drain voltage
Shift register clock voltage
Reset gate clock voltage
Reset feed-through level clamp
clock voltage
Transfer gate clock voltage
Operating ambient temperatureNote
Storage temperature
Symbol
VOD
Vφ 1, Vφ 2, Vφ 1L
Vφ RB
Vφ CLB
Vφ TG1 to Vφ TG3
TA
Tstg
Note Use at the condition without dew condensation.
Ratings
−0.3 to +15
−0.3 to +8
−0.3 to +8
−0.3 to +8
−0.3 to +8
0 to +60
−40 to +70
Unit
V
V
V
V
V
°C
°C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (TA = +25°C)
Parameter
Output drain voltage
Shift register clock high level
Shift register clock low level
Reset gate clock high level
Reset gate clock low level
Reset feed-through level clamp clock
high level
Reset feed-through level clamp clock
low level
Transfer gate clock high level
Transfer gate clock low level
Data rate
Symbol
VOD
Vφ 1H, Vφ 2H, Vφ 1LH
Vφ 1L, Vφ 2L, Vφ 1LL
Vφ RBH
Vφ RBL
Vφ CLBH
Vφ CLBL
Vφ TG1H to Vφ TG3H
Vφ TG1L to Vφ TG3L
fφ RB
Min.
11.4
4.75
−0.3
4.5
−0.3
4.5
−0.3
4.75
−0.3
−
Typ.
12.0
5.0
0
5.0
0
5.0
0
Vφ
Note
1H
0
2.0
Max.
12.6
5.5
+0.25
5.5
+0.5
5.5
+0.5
Vφ
Note
1H
+0.15
10.0
Unit
V
V
V
V
V
V
V
V
V
MHz
Note When Transfer gate clock high level (Vφ TG1H to Vφ TG3H) is higher than Shift register clock high level (Vφ 1H),
Image lag can increase.
Data Sheet S15329EJ2V0DS
5
5 Page 
µ PD8871
φ TG1 to φ TG3, φ 1, φ 2 TIMING CHART
φ TG1 to φ TG3
φ 1, φ 1L
90%
t13
90%
10%
t15
t12 t14
t16
φ2
φ 1, φ 1L
φ RB
φ CLB
(Bit clamp mode)
φ CLB
(Line clamp mode)
t17
90%
t7
90%
t22 t20
90%
10%
t9
Note 1
Note 2
90%
t18
t11
t21 t23
t19 t10
Symbol
t7
t9, t10
t11
t12
t13, t14
t15, t16
t17, t18
t19
t20, t21
t22, t23
Min.
−5 Note 3
0
10
5000
0
900
200
t12
0
0
Typ.
25
25
25
10000
50
1000
400
t12
50
350
Max.
−
−
−
50000
−
−
−
50000
−
−
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1. Set the φ RB pulse to high level during this period.
2. Stop the φ RB pulse during this period.
3. Min. of t7 shows that the φ RB and φ CLB overlap each other.
Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB.
φ 1, φ 2 cross points
φ2
φ1
φ 1L, φ 2 cross points
φ2
φ 1L
2 V or more
2 V or more
2 V or more
0.5 V or more
Remark Adjust cross points (φ 1, φ 2) and (φ 1L, φ 2) with input resistance of each pin.
Data Sheet S15329EJ2V0DS
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet UPD8871.PDF ] | |
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