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PDF LV4124W Data sheet ( Hoja de datos )
| Número de pieza | LV4124W | |
| Descripción | Single-Chip LCD Panel Drive IC | |
| Fabricantes | Sanyo Semiconductor | |
| Logotipo |  |
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Ordering number : EN6000
Monolithic Linear IC
LV4124W
Single-chip LCD panel driver IC
(Supports the ALP202 LCD panel)
Overview
The LV4124W is a LCD panel driver for use in low-
temperature polysilicon TFT LCDs that integrates an RGB
decoder, a driver, and a timing controller in a single chip.
This IC is manufactured in Bi-CMOS process and
supports the ALP202 2.0-inch color LCD panel.
Functions
• Analog block: RGB decoder/driver
• Digital block: Timing generator
Features
• Supports NTSC/PAL standard
• Supports composite, Y/C, and Y/color difference inputs
• Built-in BPF, TRAP, and DL circuits
• Sharpness function
• Dual point γ correction circuit
• Pre-charge circuit
www.DataSheet4U.com • R and B outputs delay time correction circuit
(Supports up and down and right and left inversions)
• Polarity reverse circuit
• External RGB input supported
• Line inversion supported
• Supports AC drive for the LCD panel during no signal
• Serial bus for mode setting and electric VR
Package Dimensions
unit: mm
SQFP-64
[LV4124W]
Package
• SQFP-64 plastic package
SANYO: SQFP64
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
82198RM (OT) No.6000-1/21
1 page  
LV4124W
Continued from preceding page
Parameter
Symbol
Conditions
[Chrominance Signal System]
Color adjustment
characteristics (maximum)
Color adjustment
characteristics (minimum)
GCOLMX
GCOLMN
Input SIG5 (VL = 150 mV) to (A), and input SIG2 (0 dB,
burst/chrominance phase = 180°) to (B).
Let V0, V1, and V2 be the chrominance signal amplitude
when COL = 128, COL = 255, and COL = 0, respectively.
Calculate GCOLMX = 20log (V1/V0), and GCOLMN = 20log
(V2/V0).
Ratings
min typ
+4 +6
–20
Unit
max
dB
–15 dB
Tint adjustment range
(maximum)
Tint adjustment range
(minimum)
TNTMX
TNTMN
Input SIG5 (VL = 150 mV) to (A), and input SIG2 (0 dB, with
a variable burst/chrominance phase) to (B).
Let θ 0, θ 1, and θ 2 be the phases when the T41 output
amplitude is minimum when TINT = 128, TINT = 255, and
TINT = 0, respectively.
Calculate TNTMX = θ1 – θ0, and TNTMN = θ2 – θ0.
–30
30
–40
40
deg
deg
Killer operating input level
ACKN
ACKP
Input SIG5 (VL = 150 mV) to (A), and to (B),
input SIG2 (with a variable level,
burst/chrominance phase = 180°, and also
burst/chrominance phase = ±135°).
Measure the T41 output amplitude.
Gradually lower the SIG3 level (amplitude) until
the killer function operates and measure that
level.
NTSC
PAL
–36 30 dB
–33 –27 dB
Demodulator output
www.DataSheet4U.com amplitude ratio (NTSC)
VRBN
VGBN
Input SIG5 (VL = 150 mV) to (A), and input SIG3 (0 dB) to
(B).
Modify the chrominance signal phase, let VB be the
maximum amplitude of the T41 chrominance demodulated
signal, let VG be the maximum amplitude of the T44
chrominance demodulated signal, and let VR be the
maximum amplitude of the T46 chrominance demodulated
signal
Calculate VRBN = VR/VB and VGBN = VG/VB.
0.53
0.63
0.73 –
0.25
0.32
0.39 –
Input SIG5 (VL = 150 mV) to (A), and input SIG3 (0 dB) to
θ RBN
(B).
Modify the chrominance signal phase, let θ B be the phase
99 109 119 deg
Demodulator output phase
difference (NTSC)
at the maximum amplitude of the T41 chrominance
demodulated signal, let θ G be the phase at the maximum
amplitude of the T44 chrominance demodulated signal, and
θ GBN
let θ R be the phase at the maximum amplitude of the T46
chrominance demodulated signal.
230 242 254 deg
Calculate θ RBN = θ R – θ B and θ GBN = θ G – θ B.
Demodulator output
amplitude ratio (PAL)
VRBP
VGBP
Input SIG5 (VL = 150 mV) to (A), and input SIG3 (0 dB) to
(B).
Modify the chrominance signal phase, let VB be the
maximum amplitude of the T41 chrominance demodulated
signal, let VG be the maximum amplitude of the T44
chrominance demodulated signal, and let VR be the
maximum amplitude of the T46 chrominance demodulated
signal
Calculate VRBP = VR/VB and VGBP = VG/VB.
0.65
0.75
0.85 –
0.33
0.40
0.47 –
Input SIG5 (VL = 150 mV) to (A), and input SIG3 (0 dB) to
(B).
θ RBP Modify the chrominance signal phase, let θ B be the phase 80 90 100 deg
Demodulator output phase
difference (PAL)
at the maximum amplitude of the T41 chrominance
demodulated signal, let θ G be the phase at the maximum
amplitude of the T44 chrominance demodulated signal, and
θ GBP
let θ R be the phase at the maximum amplitude of the T46
chrominance demodulated signal.
232 244 256 deg
Calculate θ RBP = θ R – θ B and θ GBP = θ G – θ B.
No.6000-5/21
5 Page 
Continued from preceding page.
Pin No.
Pin
Pin voltage
6 EXTR
7 EXTG
–
8 EXTB
LV4124W
I/O Input handling
Pin function
These pins are used to input
external digital signals.
There are two threshold
levels: Vth1 (about 1.0 V) and
Vth2 (about 2.0 V). If one of
I the RGB signal exceeds Vth1,
then all of the RGB outputs
are set to the black level, and
the output only goes to the
white level when the input
exceeds Vth2.
37 FBPCD
42 FBB
45 FBG
2.5 V
47 FBR
O
Feedback circuit smoothing
capacitor connections. These
circuits are used to control the
DC levels in the RGB and
PCD outputs.
Since these are high-
impedance circuits, capacitors
with low leakage must be
used.
www.DataSheet4U.com
38 GNDPCD
0V
Ground for the PCD circuit
Units (Capacitors: F, Resistors: Ω)
Equivalent circuit
39 PCD
6.0 V
O
PCD output
40 VCCPCD
12 V
12V system power supply
used for the PCD circuit.
Use the same potential as
used for VCC2.
Continued on next page.
No.6000-11/21
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet LV4124W.PDF ] | |
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