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PDF LP2994M Data sheet ( Hoja de datos )
| Número de pieza | LP2994M | |
| Descripción | DDR Termination Regulator | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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May 2002
LP2994
DDR Termination Regulator
General Description
The LP2994 regulator is designed to provide a linear solution
to meet the JEDEC SSTL-2 and SSTL-3 specifications (Se-
ries Stub Termination Logic) for active termination of DDR-
SDRAM. The device utilizes an internal operational amplifier
to provide linear regulation of VTT without the need for
expensive external components. The output stage prevents
shoot through while delivering 1.5A continuous current and
maintaining excellent load regulation. The LP2994 also in-
corporates an active low shutdown pin to tri-state the output
during Suspend To Ram (STR) states.
Patents Pending
Features
n Source and sink current
n Low external component count
n Independent analog and power rails
n Linear topology
n Small package SO-8
n Low cost and easy to use
n Shutdown pin
Applications
n SSTL-2
n SSTL-3
n DDR-SDRAM Termination
n DDR-II Termination
Typical Application Circuit
FIGURE 1. SSTL-2 VTT Termination
20045904
© 2002 National Semiconductor Corporation DS200459
www.national.com
1 page  
Typical Performance Characteristics (Continued)
VIL and VIHvs AVIN (25˚C)
Maximum Sourcing Current vs AVIN
(VDDQ = 2.5V, PVIN = 1.8V)
20045920
Maximum Sourcing Current vs AVIN
(VDDQ = 2.5V, PVIN = 2.5V)
20045921
Maximum Sourcing Current vs AVIN
(VDDQ = 2.5V, PVIN = 3.3V)
20045922
Maximum Sinking Current vs AVIN
(VDDQ = 2.5V)
20045923
Maximum Sourcing Current vs AVIN
(VDDQ = 1.8V, PVIN = 1.8V)
20045924
5
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5 Page 
Typical Application Circuits (Continued)
20045906
FIGURE 6. SSTL-2 Implementation with higher voltage rails
DDR-II Applications
With the separate VDDQ pin and an internal resistor divider it
is possible to use the LP2994 in applications utilizing DDR-II
memory. Figure 7 and Figure 8 show several implementa-
tions of recommended circuits with output curves displayed
in the Typical Performance Characteristics. Figure 7 shows
the recommended circuit configuration for DDR-II applica-
tions. The output stage is connected to the 1.8V rail and the
AVIN pin can be connected to either a 3.3V or 5V rail.
FIGURE 7. Recommended DDR-II Termination
20045907
If it is not desirable to use the 1.8V rail it is possible to
connect the output stage to a 3.3V rail. Care should be taken
to not exceed the maximum junction temperature as the
thermal dissipation increases with lower VTT output voltages.
For this reason, it is not recommended to power PVIN off a
rail higher than the nominal 3.3V. The advantage of this
configuration is that it has the ability to source and sink a
higher maximum continuous current.
20045908
FIGURE 8. DDR-II Termination with higher voltage rails
If standards other than SSTL-2 are required, such as
SSTL-3, it may be necessary to use a different scaling factor
than 0.5 times VDDQ for regulating the output voltage. Sev-
eral options are available to scale the output to any voltage
required. One method is to level shift the output by using
feedback resistors from VTT to the VSENSE pin. This has
been illustrated in Figure 9 and Figure 10. Figure 9 shows
11 www.national.com
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| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet LP2994M.PDF ] | |
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