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부품번호 | JZ4730 기능 |
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기능 | 32-Bit Microprocessor | ||
제조업체 | Ingenic | ||
로고 | |||
www.DataSheet4U.com
Jz4730
32 Bits Microprocessor
Data Sheet
Revision: 1.1
Date: Aug. 2006
www.DataShCeeotn4Ut.ecnomt
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Jz4730 32 Bits Microprocessor Data Sheet, Revision 1.0
Copyright® 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
4페이지 www.DataSheet4U.com
Overview
― Six chip-select pin for static memory, each can be configured separately
― Support 8, 16 or 32 bits data width
― The size and base address of static memory banks are programmable
• NAND Flash interface
― Support on CS3, sharing with static memory bank 3
― Support all 8-bit/16-bit NAND Flash devices regardless of density and organization
― Hardware ECC generation
― Support automatic boot up from NAND Flash devices
• Synchronous DRAM Interface
― 2 banks with programmable size and base address
― 32-bit and 16-bit data bus width is supported
― Multiplexes row/column addresses according to SDRAM capacity
― Two-bank or four-bank SDRAM is supported
― Supports auto-refresh and self-refresh functions
― Supports power-down mode to minimize the power consumption of SDRAM
― Supports page mode
• PC Card Interface
― Fully compliant with the release of March 1997 of PC Card standard (16-bit PC
Card)
― DMA transfer support
― Supports two PCMCIA or CF socket
• Direct Memory Access Controller
― Eight independent DMA channels
― Transfer data units: 8-bit, 16-bit, 32-bit, 16-byte or 32-byte
― Transfer requests can be: auto-request within DMA; on-chip peripheral module
request; and external request
― Interrupt on transfer completion or transfer error
― Supports two transfer modes: single mode or block mode
• The Jz4730 processor system supports little endian only
1.2.4
Inter-chip Connectivity
• I2C bus interface
― Only supports single master mode
― Supports I2C standard-mode and F/S-mode up to 400 kHz
― Double-buffered for receiver and transmitter
― Supports general call address and START byte format after START condition
• Synchronous serial interface
― Supports three formats: TI’s SSP, National Microwire, and Motorola’s SPI
― Configurable 2 - 17 (or multiples of them) bits data transfer
― Full-duplex/transmit-only/receive-only operation
― Supports normal transfer mode or Interval transfer mode
― Programmable transfer order: MSB first or LSB first
― 17-bit width, 16-level deep transmit-FIFO and receive-FIFO
Jz4730 32 Bits Microprocessor Data Sheet, Revision 1.0
Copyright® 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
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부품번호 | 상세설명 및 기능 | 제조사 |
JZ4730 | 32-Bit Microprocessor | Ingenic |
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