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WV3EG232M64EFSU-D4 데이터시트 PDF




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부품번호 WV3EG232M64EFSU-D4 기능
기능 512MB - 2x32Mx64 DDR SDRAM
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WV3EG232M64EFSU-D4 데이터시트, 핀배열, 회로
White Electronic Designs WV3EG232M64EFSU-D4
ADVANCED*
512MB – 2x32Mx64 DDR SDRAM, UNBUFFERED, w/PLL, FBGA
FEATURES
Fast data transfer rate: PC-2100 and PC-2700
Clock speeds of 133 MHz and 166 MHz
Two data transfers per clock cycle
Supports ECC error detection and correction
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2 and 2.5 (clock)
Programmable Burst Length (2, 4 or 8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect (SPD) with EEPROM
Dual Rank
Power supply: VCC = VCCQ = +2.5V ±0.2V (133 and
166MHz)
Gold edge contacts
200 pin, small-outline, SO-DIMM package
• PCB height option:
31.75 mm (1.25”)
NwOwTEw: .CDoanstaulSt fahcetoeryt4foUr a.cvaoilmability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
DESCRIPTION
The WV3EG232M64EFSU is a 2x32Mx64 Double Data
Rate SDRAM memory module based on 256Mb DDR
SDRAM components. The module consists of sixteen
32Mx8 4 banks DDR SDRAMs in FBGA packages
mounted on a 200 pin FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
Clock Speed
CL-tRCD-tRP
OPERATING FREQUENCIES
DDR333@CL=2.5
166MHz
2.5-3-3
DDR266@CL=2
133MHz
2-2-2
DDR266@CL=2.5
133MHz
2.5-3-3
April 2005
Rev. 0
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com




WV3EG232M64EFSU-D4 pdf, 반도체, 판매, 대치품
White Electronic Designs WV3EG232M64EFSU-D4
ADVANCED
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VCC supply relative to Vss
Voltage on VCCQ supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
VIN, VOUT
VCC
VCCQ
TSTG
PD
IOS
Value
-0.5 ~ 3.6
-1.0 ~ 3.6
-0.5 ~ 3.6
-55 ~ +150
16
50
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Unit
V
V
V
°C
W
mA
DC OPERATING CONDITIONS
TA = 0°C to 70°C
Parameter
Supply voltage(for device with a nominal VCC of 2.5V)
I/O Supply voltage
I/O Reference voltage
I/O Termination voltage(system)
Input logic high voltage
Input logic low voltage
Input Voltage Level, CK and CK# inputs
Input Differential Voltage, CK and CK# inputs
Input crossing point voltage, CK and CK# inputs
Input leakage current
Output leakage current
Output High Current(Normal strengh driver); VOUT = VTT + 0.84V
Output High Current(Normal strengh driver); VOUT = VTT - 0.84V
wOwutwpu.Dt HaitgahSChuerreetn4t(UHa.clfosmtrengh driver); VOUT = VTT + 0.45V
Output High Current(Half strengh driver); VOUT = VTT - 0.45V
Symbol
VCC
VCCQ
VREF
VTT
VIH(DC)
VIL(DC)
VIN(DC)
VID(DC)
VIX(DC)
II
IOZ
IOH
IOL
IOH
IOL
Min
2.3
2.3
VCCQ/2-50mV
VREF-0.04
VREF+0.15
-0.3
-0.3
0.3
1.15
-2
-5
-16.8
16.8
-9
9
Max
2.7
2.7
VCCQ/2+50mV
VREF+0.04
VCCQ+0.3
VREF-0.15
VCCQ+0.3
VCCQ+0.6
1.35
2
5
Unit
v
V
V
V
V
V
V
V
V
uA
uA
mA
mA
mA
mA
Note
1
2
4
4
3
5
Notes:
1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The DRAM must
accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of ≤ 3nH.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF.
3. VID is the magnitude of the difference between the input level on CK and the input level on CK#.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative
to a VREF envelop that has been bandwidth limited to 200MHZ.
5. The value of VIX is expected to equal 0.5*VCCQ of the transmitting device and must track variations in the dc level of the same.
CAPACITANCE
VCC = 2.5, VCCQ = 2.5V, TA = 25 C, f = 1MHz
Parameter
Symbol
Min
Max
Unit
Input capacitance (A0 ~ A12, BA0 ~ BA1,RAS#, CAS#, WE#)
CIN1
38
47
pF
Input capacitance (CKE0,CKE1)
CIN2 38 47 pF
Input capacitance ( CS0#, CS1#)
CIN3 36 44 pF
Input capacitance ( CK0, CK0#)
CIN4 36 40 pF
Input capacitance (DM0~DM7)
CIN5 12 14 pF
Data & DQS input/output capacitance (DQ0~DQ63)
COUT1
12
14
pF
April 2005
Rev. 0
4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

4페이지










WV3EG232M64EFSU-D4 전자부품, 판매, 대치품
White Electronic Designs WV3EG232M64EFSU-D4
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC
OPERATING CONDITIONS
0°C ≤ TA ≤ +70°C; VCC = VCCQ = +2.5V ±0.2V
AC Operating Test Conditions
Parameter
335
Symbol
Min Max
262
Min Max
265
Min Max
Unit Note
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Read command
Col. address to Col. address delay
Clock cycle time
tRC 60 65 65 ns
tRFC 72 75 75 ns
tRAS 42 70K 45 120K 45 120K ns
tRCD 18 20 20 ns
tRP 18 20 20 ns
tRRD 12 15 15 ns
tWR 15 15 15 ns
tWTR 1 1 1 tCK
tCCD 1 1 1 tCK
CL=2.0
7.5 12 7.5 12 10 12 ns
tCK
CL=2.5
6 12 7.5 12 7.5 12 ns
5
5
Clock high level width
Clock low level width
DQS-out access time from CK/CK#
Output data access time from CK/CK#
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS falling edge to CK rising-setup time
wDwQwS.fDalalintgaSedhgeeeftr4omU.CcKomrising-hold time
DQS-in high level width
DQS-in low level width
DQS-in cycle time
Address and Control Input setup time(fast)
Address and Control Input hold time(fast)
Address and Control Input setup time(slow)
Address and Control Input hold time(slow)
Data-out high impedence time from CK/CK#
Data-out low impedence time from CK/CK#
Input Slew Rate(for input only pins)
Input Slew Rate(for I/O pins)
Output Slew Rate(x4,x8)
Output Slew Rate Matching Ratio(rise to fall)
tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK
tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK
tDQSCK -0.6
+0.6 -0.75 +0.75 -0.75 +0.75
ns
tAC -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns
tDQSQ – 0.45 – 0.5 – 0.5 ns
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
tDQSS 0.75 1.25 0.75 1.25 0.75 1.25
tCK
tWPRES
0
0
0 ns
tWPRE 0.25 0.25 0.25
tCK
tDSS 0.2 0.2 0.2 tCK
tDSH 0.2 0.2 0.2 tCK
tDQSH
0.35
0.35
0.35
tCK
tDQSL
0.35
0.35
0.35
tCK
tDSC 0.9 1.1 0.9 1.1 0.9 1.1 tCK
tIS 0.75
0.9
0.9
ns
tIH 0.75
0.9
0.9
ns
tIS 0.8 1.0 1.0 ns
tIH 0.8 1.0 1.0 ns
tHZ -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns
tLZ -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns
tSL(I) 0.5 0.5 0.5 V/ns
tSL(IO)
0.5
0.5
0.5 V/ns
tSL(O)
1.0
4.5
1.0
4.5
1.0
4.5 V/ns
tSLMR
0.67
1.5
0.67
1.5
0.67
1.5
5
2
6
6
6
6
6
7
AC Timing Parameters are based on Samsung components. Other DRAM Manufacturers parameters may be different.
April 2005
Rev. 0
7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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WV3EG232M64EFSU-D4

512MB - 2x32Mx64 DDR SDRAM

White Electronic Designs
White Electronic Designs

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