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부품번호 | WV3HG2128M72EEU-D6 기능 |
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기능 | 2GB - 2x128Mx72 DDR2 SDRAM UNBUFFERED DIMM | ||
제조업체 | White Electronic Designs | ||
로고 | |||
White Electronic Designs WV3HG2128M72EEU-D6
ADVANCED*
2GB – 2x128Mx72 DDR2 SDRAM UNBUFFERED DIMM
FEATURES
Unbuffered 240-pin, dual in-line memory module
Fast data transfer rates: PC2-6400*, PC2-5300*,
PC2-4300 and PC2-3200
VCC = VCCQ = 1.8V
VCCSPD = +1.7V to +3.6V
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
DLL to align DQ and DQS transitions with CK
Multiple internal device banks for concurrent
operation
Supports duplicate output strobe (RDQS/RDQS#)
Programmable CAS# latency (CL): 3, 4, 5* and 6*
Adjustable data-output drive strength
On-die termination (ODT)
Serial Presence Detect (SPD) with EEPROM
Auto & self refresh (64ms/8,192 cycle refresh)
Gold edge contacts
Dual Rank
RoHS compliant
www.DPataaSchkeaegt4eU.ocpomtion
• 240 Pin DIMM
• 30.00mm (1.181") TYP
DESCRIPTION
The WV3HG2128M72EEU is a 2x128Mx72 Double Data
Rate DDR2 SDRAM high density module. This memory
module consists of eighteen 128Mx8 bit with 4 banks
DDR2 Synchronous DRAMs in FBGA packages, mounted
on a 240-pin DIMM FR4 substrate.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
• Parity function
Clock Speed
CL-tRCD-tRP
* Consult factory for availability
PC2-6400*
400MHz
6-6-6
OPERATING FREQUENCIES
PC2-5300*
333MHz
5-5-5
PC2-4300
266MHz
4-4-4
PC2-3200
200MHz
3-3-3
August 2006
Rev. 1
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs WV3HG2128M72EEU-D6
ADVANCED
DC OPERATING CONDITIONS
All voltages referenced to VSS
Parameter
Symbol Min Typical Max
Unit Notes
Supply Voltage
I/O Reference Voltage
I/O Termination Voltage
SPD Supply Voltage
VCC
VREF
VTT
VCCSPD
1.7
0.49 x VCC
VREF-0.04
1.7
1.8
0.50 x VCC
VREF
-
1.9
0.51 x VCC
VREF+0.04
3.6
V
V
V
V
3
1
2
Notes:
1 VREF is expected to equal VCC/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/-1 percent of the
DC value. Peak-to-peak AC noise on VREF may not exceed +/-2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF.
3. VCCQ of all IC's are tied to VCC.
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
VIN, VOUT
TSTG
Parameter
Voltage on VCC pin relative to VSS
Voltage on any pin relative to VSS
Storage Temperature
IL
Input leakage current; Any input 0V<VIN<VCC; VREF input
0V,VIN,0.95V; Other pins not under test = 0V
IOZ Output leakage current; 0V<VIN<VCC; DQs and ODT are disable
w w w IV.REDF a t a VSREFhleaekagee ct ur4renUt; V.REcF =oVamlid VREF level
Command/Address,
RAS#, CAS#, WE#,
CS#, CKE
CK, CK#
DM
DQ, DQS, DQS#
Min
-0.5
-0.5
-55
-90
-45
-30
-10
-10
-36
Max Units
2.3 V
2.3 V
100 °C
90 µA
45 µA
30 µA
10 µA
10 µA
36 µA
INPUT/OUTPUT CAPACITANCE
TA = 25°C, f = 100MHz
Parameter
Input Capacitance (A0-A13, BA0~BA2, RAS#, CAS#, WE#)
Input Capacitance (CKE0, CKE1), (ODT0, ODT1)
Input Capacitance (CS0#, CS1#))
Input Capacitance (CK0, CK0#-CK2, CK2#)
Input Capacitance (DQS0~DQS8), (DM0-DM8)
Input Capacitance (DQ0~DQ63), (CB0~CB7)
Symbol
Min
Max
Unit
CIN1 22 40 pF
CIN2 13 22 pF
CIN3 13 22 pF
CIN4 10 16 pF
CIN5 (665)
9
11 pF
CIN5 (534, 403)
9
12 pF
COUT (665)
9
11 pF
COUT (534, 403)
9
12 pF
August 2006
Rev. 1
4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
4페이지 White Electronic Designs WV3HG2128M72EEU-D6
ADVANCED
AC TIMING PARAMETERS & SPECIFICATIONS
AC CHARACTERISTICS
806 665 534 403
PARAMETER
CL = 6
Clock cycle time
CL = 5
CL = 4
CL = 3
CK high-level width
CK low-level width
Half clock period
Clock jitter
DQ output access time from CK/CK#
Data-out high-impedance window from
CK/CK#
Data-out low-impedance window from
CK/CK#
DQ and DM input setup time relative to
DQS
DQ and DM input hold time relative to DQS
DQ and DM input pulse width (for each
input)
Data hold skew factor
DQ…DQS hold, DQS to first DQ to go
nonvalid, per access
Data valid output window (DVW)
DQS input high pulse width
DQS input low pulse width
www.DaDtaQSSheoeutt4pUut.caocmcess time from CK/CK#
DQS falling edge to CK rising … setup time
DQS falling edge from CK rising … hold
time
DQS…DQ skew, DQS to last DQ valid, per
group,
per access
DQS read preamble
DQS read postamble
DQS write preamble setup time
DQS write preamble
DQS write postamble
Write command to first DQS latching
transition
Address and control input pulse width for
each input
Address and control input setup time
Address and control input hold time
Address and control input hold time
SYMBOL
tCK (6)
tCK (5)
tCK (4)
tCK (3)
tCH
tCL
tHP
tJIT
tAC
tHZ
tLZ
tDS
tDH
tDIPW
tQHS
tQH
tDVW
tDQSH
tDQSL
tDQSCK
tDSS
tDSH
tDQSQ
tRPRE
tRPST
tWPRES
tWPRE
tWPST
tDQSS
tIPW
tIS
tIH
tCCD
MIN
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
MAX
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
MIN MAX MIN MAX MIN MAX
3,000
3,750
5,000
0.45
0.45
MIN(tCH,tCL)
-125
-450
8,000
8,000
8,000
0.55
0.55
125
+450
3,750
5,000
0.45
0.45
MIN(tCH,tCL)
-125
-500
8,000
8,000
0.55
0.55
125
+500
5,000
5,000
0.45
0.45
MIN(tCH,tCL)
-125
-600
8,000
8,000
0.55
0.55
125
+600
tAC(MAX)
tAC(MAX)
tAC(MAX)
TBD tAC(MIN) tAC(MAX) tAC(MIN) tAC(MAX) tAC(MIN) tAC(MAX)
TBD 100 100 150
TBD 225 225 275
TBD 0.35 0.35 0.35
TBD 340 400 450
TBD tHP - tQHS
tHP - tQHS
tHP - tQHS
TBD tQH - tDQSQ
tQH - tDQSQ
tQH - tDQSQ
TBD 0.35 0.35 0.35
TBD 0.35 0.35 0.35
TBD -400 +400 -450 +450 -500 +500
TBD 0.2 0.2 0.2
TBD 0.2 0.2 0.2
TBD
240 300 350
TBD 0.9 1.1 0.9 1.1 0.9 1.1
TBD 0.4 0.6 0.4 0.6 0.4 0.6
TBD 0 0 0
TBD 0.35 0.35 0.35
TBD 0.4 0.6 0.4 0.6 0.4 0.6
TBD WL- WL+ WL- WL+ WL- WL+
0.25 0.25 0.25 0.25 0.25 0.25
TBD 0.6 0.6 0.6
TBD 200 250 250
TBD 275 375 475
TBD 2 2 2
* AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
Continued on next page
UNIT
ps
ps
ps
ps
tCK
tCK
ps
ps
ps
ps
ps
tCK
ps
ps
ns
tCK
tCK
ps
tCK
tCK
ps
tCK
tCK
ps
tCK
tCK
tCK
tCK
ps
ps
tCK
August 2006
Rev. 1
7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
7페이지 | |||
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WV3HG2128M72EEU-D6 | 2GB - 2x128Mx72 DDR2 SDRAM UNBUFFERED DIMM | White Electronic Designs |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |