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WV3HG264M72EER-PD4 데이터시트 PDF




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기능 1GB - 2x64Mx72 DDR2 SDRAM REGISTERED
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WV3HG264M72EER-PD4 데이터시트, 핀배열, 회로
White Electronic Designs WV3HG264M72EER-PD4
ADVANCED*
1GB – 2x64Mx72 DDR2 SDRAM REGISTERED, SO-DIMM, w/PLL
FEATURES
Registered 200-pin (SO-DIMM), Small-Outline dual
in-line memory module
Support ECC detection and correction
Fast data transfer rates: PC2-6400*, PC2-5300*,
PC2-4200 and PC2-3200
VCC = VCCQ = 1.8V ±0.1V
VCCSPD = 1.7V to 3.6V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
Multiple internal device banks for concurrent
operation
Differential clock inputs (CK, CK#)
Programmable CAS# latency (CL): 3, 4, 5*, and 6*
Posted CAS# additive latency: 0, 1, 2, 3 and 4
On-die termination (ODT)
7.8µs average periodic refresh interval
Serial Presence Detect (SPD) with EEPROM
Utilizes 512Mb DDR2 SDRAM components
Auto & self refresh (64ms: 8,192 cycle refresh)
wwwG.DoaltdaSehdegeet4cUo.ncotamcts
Dual Rank
RoHS compliant
JEDEC proposed Pin-out
Package
• 200 Pin SO-DIMM: 30.00mm (1.181") TYP.
DESCRIPTION
The WV3HG264M72EER is a 2x64Mx72 Double Data
Rate DDR2 SDRAM high density module. This memory
module consists of eighteen 64Mx8 bit DDR2 Synchronous
DRAMs in FBGA packages, mounted on a 200-pin SO-
DIMM FR4 substrate.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
Clock Speed
CL-tRCD-tRP
* Consult factory for availability
PC2-3200
200MHz
3-3-3
OPERATING FREQUENCIES
PC2-4200
266MHz
4-4-4
PC2-5300*
333MHz
5-5-5
PC2-6400*
400MHz
6-6-6
April 2006
Rev. 2
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com




WV3HG264M72EER-PD4 pdf, 반도체, 판매, 대치품
White Electronic Designs WV3HG264M72EER-PD4
ADVANCED
Symbol
VCC
VIN, VOUT
TSTG
IL
IOZ
IVREF
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on VCC pin relative to VSS
Voltage on any pin relative to VSS
Storage Temperature
Input leakage current; Any input 0V<VIN<VCC; VREF input
0V,VIN,0.95V; Other pins not under test = 0V
Output leakage current; 0V<VIN<VCC; DQs and ODT are disable
VREF leakage current; VREF = Valid VREF level
Command/Address,
RAS#, CAS#, WE#,
CK, CK#
DM
DQ, DQS, DQS#
Min
-0.5
-0.5
-55
-5
-10
-10
-10
-36
Max Units
2.3 V
2.3 V
100 °C
5 µA
10 µA
10 µA
10 µA
36 µA
DC OPERATING CONDITIONS
All voltages referenced to VSS
Parameter
Symbol Min Typical Max
Unit Notes
Supply Voltage
I/O Reference Voltage
I/O Termination Voltage
SPD Supply Voltage
VCC
VREF
VTT
VCCSPD
1.7
0.49 x VCC
VREF-0.04
1.7
1.8
0.50 x VCC
VREF
-
1.9
0.51 x VCC
VREF+0.04
3.6
V
V
V
V
3
1
2
Notes:
1 VREF is expected to equal VCC/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/-1 percent of the
DC value. Peak-to-peak AC noise on VREF may not exceed +/-2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF.
3. VCCQ of all IC's are tied to VCC.
www.DataSheet4U.com
OPERATING TEMPERATURE CONDITION
Parameter
Symbol
Rating
Units
Notes
Operating Case Temperature (commercial)
TOPER
0 to +85°C
°C
1, 2
NOTE:
1. Operation temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD51.2
2. At 0 to +85°C, operation temperature range, all DRAM specification will be supported.
April 2006
Rev. 2
4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

4페이지










WV3HG264M72EER-PD4 전자부품, 판매, 대치품
White Electronic Designs WV3HG264M72EER-PD4
ADVANCED
AC TIMING PARAMETERS & SPECIFICATIONS
VCC = +1.8V ± 0.1V
AC CHARACTERISTICS
806 665 534 403
PARAMETER
SYMBOL
CL = 6
tCK (6)
Clock cycle time
CL = 5
CL = 4
tCK (5)
tCK (4)
CL = 3
tCK (3)
CK high-level width
tCH
CK low-level width
tCL
Half clock period
tHP
Clock jitter
tJIT
DQ output access time from CK/CK#
tAC
Data-out high-impedance window from
CK/CK#
tHZ
Data-out low-impedance window from
CK/CK#
tLZ
DQ and DM input setup time relative to
DQS
tDS
DQ and DM input hold time relative to DQS tDH
DQ and DM input pulse width (for each
input)
tDIPW
Data hold skew factor
tQHS
DQ…DQS hold, DQS to first DQ to go
nonvalid, per access
tQH
Data valid output window (DVW)
tDVW
DQS input high pulse width
tDQSH
DQS input low pulse width
tDQSL
www.DDQatSaoSuhtpeuetta4cUce.cssotmime from CK/CK#
tDQSCK
DQS falling edge to CK rising … setup time tDSS
DQS falling edge from CK rising … hold
time
tDSH
DQS…DQ skew, DQS to last DQ valid, per
group,
per access
tDQSQ
DQS read preamble
tRPRE
DQS read postamble
tRPST
DQS write preamble setup time
tWPRES
DQS write preamble
tWPRE
DQS write postamble
tWPST
Write command to first DQS latching
transition
tDQSS
Address and control input pulse width for
each input
tIPW
Address and control input setup time
tIS
Address and control input hold time
tIH
Address and control input hold time
tCCD
MIN
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
MAX
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
MIN MAX MIN MAX MIN MAX
3,000 8,000
3,750 8,000 3,750 8,000 5,000 8,000
5,000 8,000 5,000 8,000 5,000 8,000
0.45 0.55 0.45 0.55 0.45 0.55
0.45 0.55 0.45 0.55 0.45 0.55
MIN(tCH,tCL)
MIN(tCH,tCL)
MIN(tCH,tCL)
-125 125 -125 125 -125 125
-450 +450 -500 +500 -600 +600
tAC(MAX)
tAC(MAX)
tAC(MAX)
TBD tAC(MIN) tAC(MAX) tAC(MIN) tAC(MAX) tAC(MIN) tAC(MAX)
TBD 100 100 150
TBD 225 225 275
TBD 0.35 0.35 0.35
TBD 340 400 450
TBD tHP - tQHS
tHP - tQHS
tHP - tQHS
TBD tQH - tDQSQ
tQH - tDQSQ
tQH - tDQSQ
TBD 0.35 0.35 0.35
TBD 0.35 0.35 0.35
TBD -400 +400 -450 +450 -500 +500
TBD 0.2 0.2 0.2
TBD 0.2 0.2 0.2
TBD
240 300 350
TBD 0.9 1.1 0.9 1.1 0.9 1.1
TBD 0.4 0.6 0.4 0.6 0.4 0.6
TBD 0 0 0
TBD 0.35 0.35 0.35
TBD 0.4 0.6 0.4 0.6 0.4 0.6
TBD WL- WL+ WL- WL+ WL- WL+
0.25 0.25 0.25 0.25 0.25 0.25
TBD 0.6 0.6 0.6
TBD 200 250 350
TBD 275 375 475
TBD 2 2 2
* AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
Continued on next page
UNIT
ps
ps
ps
ps
tCK
tCK
ps
ps
ps
ps
ps
tCK
ps
ps
ns
tCK
tCK
ps
tCK
tCK
ps
tCK
tCK
ps
tCK
tCK
tCK
tCK
ps
ps
tCK
April 2006
Rev. 2
7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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WV3HG264M72EER-PD4

1GB - 2x64Mx72 DDR2 SDRAM REGISTERED

White Electronic Designs
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